- 30 12月, 2021 1 次提交
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由 Lingrui98 提交于
* timing: use single ported SRAMs, invalidating read responses on write * performance: -- shortening history length to accelerate training -- use a predictor to reduce s2_redirects on FTB not hit
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- 26 12月, 2021 2 次提交
- 24 12月, 2021 5 次提交
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 Jay 提交于
* IPrefetch: fix prefetchPtr stop problem * This problem happens because prefetchPtr still exits when close IPrefetch * Fix PMP req port still be occupied even when ICache miss * Shut down IPrefetch * IPrefetch: fix Hint not set PreferCache bit * bump HuanCun
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由 Lingrui98 提交于
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- 23 12月, 2021 14 次提交
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由 Jay 提交于
* IPrefetch: fix prefetchPtr stop problem * This problem happens because prefetchPtr still exits when close IPrefetch * Fix PMP req port still be occupied even when ICache miss * Shut down IPrefetch * IPrefetch: fix Hint not set PreferCache bit * bump HuanCun
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由 Lingrui98 提交于
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由 JinYue 提交于
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由 JinYue 提交于
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由 JinYue 提交于
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由 JinYue 提交于
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由 JinYue 提交于
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由 Lingrui98 提交于
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由 Lingrui98 提交于
* block reads when ittage writes * reset ras on reset so that it would not provide random addresses
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由 JinYue 提交于
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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- 22 12月, 2021 6 次提交
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由 JinYue 提交于
* This problem happens because prefetchPtr still exits when close IPrefetch * Fix PMP req port still be occupied even when ICache miss
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由 William Wang 提交于
* mem: optimize missq reject to lq timing DCache replay request is quite slow to generate, as it need to compare load address with address in all valid miss queue entries. Now we delay the usage of replay request from data cache. Now replay request will not influence normal execution flow until load_s3 (1 cycle after load_s2, load result writeback to RS). Note1: It is worth mentioning that "select refilling inst for load writeback" will be disabled if dcacheRequireReplay in the last cycle. Note2: ld-ld violation or forward failure will let an normal load inst replay from fetch. If TLB hit and ld-ld violation / forward failure happens, we write back that inst immediately. Meanwhile, such insts will not be replayed from rs. * dcache: compare probe block addr instead of full addr
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由 William Wang 提交于
* difftest: bump difftest to support --no-diff test * ci: add cacheoptest test (--no-diff)
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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- 21 12月, 2021 7 次提交
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由 William Wang 提交于
* dcache: use sram to build ecc array * MainPipe: latch s1_encTag to last until s1_fire Authored-by: Nzhanglinjuan <zhanglinjuan20s@ict.ac.cn>
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由 Yinan Xu 提交于
This commit adds an LsqEnqCtrl module to add one more clock cycle between dispatch and load/store queue. LsqEnqCtrl maintains the lqEnqPtr/sqEnqPtr and lqCounter/sqCounter. They are used to determine whether load/store queue can accept new instructions. After that, instructions are sent to load/store queue. This module decouples queue allocation and real enqueue. Besides, uop storage in load/store queue are optimized. In dispatch, only robIdx is required. Other information is naturally conveyed in the pipeline and can be stored later in load/store queue if needed. For example, exception vector, trigger, ftqIdx, pdest, etc are unnecessary before the instruction leaves the load/store pipeline.
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由 William Wang 提交于
This commit removed PriorityEncoder in sbuffer enq path. It should improve sbuffer enqueue timing.
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由 Lemover 提交于
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由 wakafa 提交于
* pma: allow r/w priv for l3-cache op mmio space * bump huancun * bump huancun * bump huancun
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由 Jay 提交于
* Add Naive Instruction Prefetch * Add instruction prefetch module in ICache * send Hint to L2 (prefetched data stores in L2) * Ftq: add prefetchPtr and prefetch interface * Fix IPrefetch PMP Port preempting problem * Fix merge conflict
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由 Li Qianruo 提交于
Refactor Trigger
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- 20 12月, 2021 5 次提交
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由 Chuanqi Zhang 提交于
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由 Jay 提交于
* ICache: raise access fault when L2 send corrupt * ICache: add ECC error connection * chores: add comments and code clean-up * ICache: raise AF when Meta/Data Parity wrong * Update Frontend.scala
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由 Li Qianruo 提交于
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由 William Wang 提交于
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由 Li Qianruo 提交于
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