L1 d cache fix bug

Dispatch: palce ALUs after MDUs (Alu should be close to int regfile)

See Tilelink spec 1.8.1 page 76.
Section 9.3.5. ProbeAck and Section 9.3.5. ProbeAckData.

conflict with prober with req_idx, not block_addr.

Optimize imm and pc

misc: eliminate difftest signal in fpga mode

datamodule template

ci: add make verilog test

Trace debug

CSR: add hardware performance counter framework

DCache: fixed sync bus between probe and LoadPipe, StorePipe and Atom…

Now, every pipe directly carries the old_repl_meta to missQueue.
So probe should block every pipe with same set req.
In case they try to replace the block probe was manipulating.

The buggy case happens this way:
1. Probe block A, which resides in set x, way y.
2. Probe has done almost everything except meta data update.
3. StorePipe handles block B, which missed in cache, so it try to
   replace set x, way y. Because Probe haven't update meta data, StorePipe
   gets a old copy of meta data, which means it will try to evict block A.
4. Probe finally update meta.
5. MissQueue accept miss request for block B from StorePipe, with the
   old_repl_meta, MissQueue tries to evict block A, although it's already
   probed out.

* values of hardware performance counters can hardly be emulated by NEMU

rs: remove buggy `if FPGAPlatform else ...` code

LoadQueueData: use separate data module

ci: add make verilog test

ci: add make verilog test