Merge pull request #432 from RISCVERS/L1DCacheFixBug

L1 d cache fix bug

src/main/scala/xiangshan/cache/dcacheWrapper.scala

@@ -398,7 +398,7 @@ class DCacheImp(outer: DCache) extends LazyModuleImp(outer) with HasDCacheParame
   // sync with prober
   missQueue.io.probe_wb_req.valid := prober.io.wb_req.fire()
   missQueue.io.probe_wb_req.bits  := prober.io.wb_req.bits
-  missQueue.io.probe_active       := prober.io.inflight_req_block_addr
+  missQueue.io.probe_active       := prober.io.inflight_req_idx
 
   //----------------------------------------
   // prober

src/main/scala/xiangshan/cache/missQueue.scala

@@ -306,7 +306,7 @@ class MissEntry(edge: TLEdgeOut) extends DCacheModule
   // if it releases the block we are trying to acquire, we don't care, since we will get it back eventually
   // but we need to know whether it releases the block we are trying to evict
   val prober_writeback_our_block = (state === s_refill_req || state === s_refill_resp ||
-    state === s_mem_finish || state === s_wait_probe_exit || state === s_send_resp || state === s_wb_req) &&
+    state === s_mem_finish || state === s_wait_probe_exit) &&
     io.probe_wb_req.valid && !io.probe_wb_req.bits.voluntary &&
     io.probe_wb_req.bits.tag === req_old_meta.tag &&
     io.probe_wb_req.bits.idx === req_idx &&

src/main/scala/xiangshan/cache/wbu.scala

@@ -126,14 +126,14 @@ class WritebackUnit(edge: TLEdgeOut) extends DCacheModule {
   val id = cfg.nMissEntries
 
   val probeResponse = edge.ProbeAck(
-    fromSource = id.U,
+    fromSource = req.source,
     toAddress = r_address,
     lgSize = log2Ceil(cfg.blockBytes).U,
     reportPermissions = req.param
   )
 
   val probeResponseData = edge.ProbeAck(
-    fromSource = id.U,
+    fromSource = req.source,
     toAddress = r_address,
     lgSize = log2Ceil(cfg.blockBytes).U,
     reportPermissions = req.param,