- 23 12月, 2021 1 次提交
-
-
由 Jay 提交于
* IPrefetch: fix prefetchPtr stop problem * This problem happens because prefetchPtr still exits when close IPrefetch * Fix PMP req port still be occupied even when ICache miss * Shut down IPrefetch * IPrefetch: fix Hint not set PreferCache bit * bump HuanCun
-
- 22 12月, 2021 1 次提交
-
-
由 William Wang 提交于
* mem: optimize missq reject to lq timing DCache replay request is quite slow to generate, as it need to compare load address with address in all valid miss queue entries. Now we delay the usage of replay request from data cache. Now replay request will not influence normal execution flow until load_s3 (1 cycle after load_s2, load result writeback to RS). Note1: It is worth mentioning that "select refilling inst for load writeback" will be disabled if dcacheRequireReplay in the last cycle. Note2: ld-ld violation or forward failure will let an normal load inst replay from fetch. If TLB hit and ld-ld violation / forward failure happens, we write back that inst immediately. Meanwhile, such insts will not be replayed from rs. * dcache: compare probe block addr instead of full addr
-
- 21 12月, 2021 5 次提交
-
-
由 William Wang 提交于
* dcache: use sram to build ecc array * MainPipe: latch s1_encTag to last until s1_fire Authored-by: Nzhanglinjuan <zhanglinjuan20s@ict.ac.cn>
-
由 Yinan Xu 提交于
This commit adds an LsqEnqCtrl module to add one more clock cycle between dispatch and load/store queue. LsqEnqCtrl maintains the lqEnqPtr/sqEnqPtr and lqCounter/sqCounter. They are used to determine whether load/store queue can accept new instructions. After that, instructions are sent to load/store queue. This module decouples queue allocation and real enqueue. Besides, uop storage in load/store queue are optimized. In dispatch, only robIdx is required. Other information is naturally conveyed in the pipeline and can be stored later in load/store queue if needed. For example, exception vector, trigger, ftqIdx, pdest, etc are unnecessary before the instruction leaves the load/store pipeline.
-
由 William Wang 提交于
This commit removed PriorityEncoder in sbuffer enq path. It should improve sbuffer enqueue timing.
-
由 wakafa 提交于
* pma: allow r/w priv for l3-cache op mmio space * bump huancun * bump huancun * bump huancun
-
由 Jay 提交于
* Add Naive Instruction Prefetch * Add instruction prefetch module in ICache * send Hint to L2 (prefetched data stores in L2) * Ftq: add prefetchPtr and prefetch interface * Fix IPrefetch PMP Port preempting problem * Fix merge conflict
-
- 20 12月, 2021 6 次提交
-
-
由 Chuanqi Zhang 提交于
-
由 Jay 提交于
* ICache: raise access fault when L2 send corrupt * ICache: add ECC error connection * chores: add comments and code clean-up * ICache: raise AF when Meta/Data Parity wrong * Update Frontend.scala
-
由 William Wang 提交于
-
由 Li Qianruo 提交于
-
由 William Wang 提交于
* dcache: let ecc error and l2 corrupt raise load af If CSR.smblockctl.cache_error_enable is disabled, ecc error and l2 corrupt will not raise any exception. * mem: enable cache error by default * mem: support store ecc check, add ecc error csr Support store / atom ecc check (early version) Add ecc error csr to distingush ecc error and other access fault Timing opt and unit tests to be added.
-
由 Jay 提交于
-
- 18 12月, 2021 1 次提交
-
-
由 Yinan Xu 提交于
-
- 17 12月, 2021 3 次提交
-
-
由 Lemover 提交于
* memblock: regnext ptw's resp * pmp: timing optimization from tlb.sram.ppn to pmp, add static pmp check long latency: tlb's sram may be slow to gen ppn, ppn to pmp may be long latency. Solution: add static pmp check. Fatal problem: pmp grain is smalled than TLB pages(4KB, 2MB, 1GB) Solution: increase pmp'grain to 4K, for 4K entries, pre-check pmp and store the result into tlb storage. For super pages, still dynamic check that translation and check. * pmp: change pmp grain to 4KB, change pma relative init config * bump ready-to-run, update nemu so for pmp grain * bump ready-to-run, update nemu so for pmp grain again update pmp unit test. The old test assumes that pmp grain is less than 512bit.
-
由 Yinan Xu 提交于
-
由 Jiawei Lin 提交于
* Change L3 to 6MB * Bump huancun
-
- 16 12月, 2021 4 次提交
-
-
由 Yinan Xu 提交于
-
由 Li Qianruo 提交于
We have singlestep already so triggers do not need to hit after inst commits
-
由 zhanglinjuan 提交于
* dcache: fix bug in ecc check * dcache: remove redundant ecc array * CacheInstruction: fix typo * dcache: fix bugs in cache instruction on ecc * MetaArray: wrap ecc array as a single module
-
由 Jay 提交于
* fix invalidTakenFault use wrong seqTarget * IFU: fix oversize bug * ctrl: mark all flushes as level.flush for frontend This commit changes how flushes behave for frontend. When ROB commits an instruction with a flush, we notify the frontend of the flush without the commit. Flushes to frontend may be delayed by some cycles and commit before flush causes errors. Thus, we make all flush reasons to behave the same as exceptions for frontend, that is, RedirectLevel.flush. * IFU: exclude lastTaken situation when judging beyond fetch Co-authored-by: NYinan Xu <xuyinan@ict.ac.cn>
-
- 15 12月, 2021 4 次提交
-
-
由 Li Qianruo 提交于
* Debug Mode: support basic difftest with spike * Debug Mode: fix some bugs Bugs fixed are: 1. All interrupts and exceptions cause debug mode to enter park loop 2. Debug interrupt ignored due to flushPipe
-
由 William Wang 提交于
-
由 Lemover 提交于
* mmpma: fix read/write io decoupled logic * pma: fix init pma config
-
由 Yinan Xu 提交于
This commit adds fused load support by bypassing LUI results to load. For better timing, detection is done at the rename stage. Imm is stored in psrc(1), psrc(0) and imm.
-
- 14 12月, 2021 5 次提交
-
-
由 Yinan Xu 提交于
-
由 Yinan Xu 提交于
This commit optimizes Dispatch2Rs timing by ignoring lsq.canAccept when sending bits to reservation stations.
-
由 Jay 提交于
* ICache: add ReplacePipe for Probe & Release * remove ProbeUnit * Probe & Release enter ReplacePipe * fix bugs when running Linux on MinimalConfig * TODO: set conflict for ReplacePipe * ICache: fix ReplacePipe invalid write bug * chores: code clean up * IFU: optimize timing * PreDecode: separate into 2 module for timing optimization * IBuffer: add enqEnable to replace valid for timing * IFU/ITLB: optimize timing * IFU: calculate cut_ptr in f1 * TLB: send req in f1 and wait resp in f2 * ICacheMainPipe: add tlb miss logic in s0 * Optimize IFU timing * IFU: fix lastHalfRVI bug * IFU: fix performance bug * IFU: optimize MMIO commit timing * IFU: optmize trigger timing and add frontendTrigger * fix compile error * IFU: fix mmio stuck bug
-
由 zhanglinjuan 提交于
-
由 Yinan Xu 提交于
This commit changes the condition to update mtval and stval. According to the RISC-V spec, when a trap is taken into M/S-mode, mtval/stval is either set to zero or written wrih exception-specific information to assist software in handling the trap. Previously in XiangShan, mtval/stval is updated depending on the current priviledge mode, which is incorrect.
-
- 13 12月, 2021 4 次提交
-
-
由 zhanglinjuan 提交于
* MissQueue: loose merging condition to ease timing stress * MissQueue: remove grant_beats * MissQueue: compare block addr, not the whole addr bits * dcache: optimize timing for generating ready to sbuffer Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>
-
由 Li Qianruo 提交于
-
由 William Wang 提交于
-
由 Jiawei Lin 提交于
* SoC: add axi4spliter * pmp: add apply method to reduce loc * pma: add PMA used in axi4's spliter * Fix package import * pma: re-write tl-pma, put tl-pma into AXI4Spliter * pma: add memory mapped pma * soc: rm dma port, rm axi4spliter, mv mmpma out of spliter * csr: clear mstatus.mprv when mstatus.mpp != ModeM at xret * csr: fix write mask for mstatus, mepc and sepc This commit fixes the write mask for mstatus, mepc and sepc. According to the RISC-V instruction manual, for RV64 systems, the SXL and UXL fields are WARL fields that control the value of XLEN for S-mode and U-mode, respectively. For RV64 systems, if S-mode is not supported, then SXL is hardwired to zero. For RV64 systems, if U-mode is not supported, then UXL is hardwired to zero. Besides, mepc[0] and sepc[0] should be hardwired to zero. * wb,load: delay load fp for one cycle * csr: add mconfigptr, but hardwire to 0 now * bump huancun * csr: add *BE to mstatusStruct which are hardwired to 0 * Remove unused files * csr: fix bug of xret clear mprv * bump difftest * ci: add unit test, xret clear mstatus.mprv when xpp is not M * bump ready-to-run * mem,atomics: delay exception info for one cycle * SoC: insert more buffers into mmio path * SoC: insert buffer between l3_xbar and l3_banked_xbar * Optimze l3->ddr path * Bump huancun Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn> Co-authored-by: NYinan Xu <xuyinan@ict.ac.cn> Co-authored-by: Nwangkaifan <wangkaifan@ict.ac.cn>
-
- 12 12月, 2021 6 次提交
-
-
由 William Wang 提交于
-
由 Jiawei Lin 提交于
* L2/L3: fix prefetch train address * HuanCun: update SRAMTemplate * Config: Keep the client dir capacity of L3 twice the L2 * Bump huancun
-
由 William Wang 提交于
-
由 William Wang 提交于
Soft prefetch will be always marked as "load hit"
-
由 Yinan Xu 提交于
All bits for stvec and mtvec are writable in XiangShan. According to the RISC-V spec, {m,s}tvec[1:0] are MODE bits. When MODE=Vectored, all synchronous exceptions into M/S mode cause the pc to be set to the address in the BASE field, whereas interrupts cause the pc to be set to the address in the BASE field plus four times the interrupt cause number. If XiangShan decides to not support vectored mode, {m,s}tvec[1:0] should be hardwired to zero.
-
由 William Wang 提交于
-