difftest: move sc_valid to AtomicsUnit (#1350)

difftest @ a541a406

-Subproject commit 3f20bf7877b9c2c000f78a49c68f5384914560ad
+Subproject commit a541a4062292dc1e0d26e543fc932fce41305871

ready-to-run @ 383fc68a

-Subproject commit 8f83b5a80b7a29be45f679a488c89e224e3a7187
+Subproject commit 383fc68ae7d7e53445c4114130dedb25d54f9369

src/main/scala/xiangshan/Bundle.scala

@@ -223,7 +223,6 @@ class MicroOp(implicit p: Parameters) extends CfCtrl {
   val robIdx = new RobPtr
   val lqIdx = new LqPtr
   val sqIdx = new SqPtr
-  val diffTestDebugLrScValid = Bool()
   val eliminatedMove = Bool()
   val debugInfo = new PerfDebugInfo
   def needRfRPort(index: Int, isFp: Boolean, ignoreState: Boolean = true) : Bool = {

src/main/scala/xiangshan/backend/rename/Rename.scala

@@ -93,7 +93,6 @@ class Rename(implicit p: Parameters) extends XSModule with HasPerfEvents {
     uop.srcState(1) := DontCare
     uop.srcState(2) := DontCare
     uop.robIdx := DontCare
-    uop.diffTestDebugLrScValid := DontCare
     uop.debugInfo := DontCare
     uop.lqIdx := DontCare
     uop.sqIdx := DontCare

src/main/scala/xiangshan/backend/rob/Rob.scala

@@ -439,7 +439,6 @@ class RobImp(outer: Rob)(implicit p: Parameters) extends LazyModuleImp(outer)
   for (wb <- exuWriteback) {
     when (wb.valid) {
       val wbIdx = wb.bits.uop.robIdx.value
-      debug_microOp(wbIdx).diffTestDebugLrScValid := wb.bits.uop.diffTestDebugLrScValid
       debug_exuData(wbIdx) := wb.bits.data
       debug_exuDebug(wbIdx) := wb.bits.debug
       debug_microOp(wbIdx).debugInfo.enqRsTime := wb.bits.uop.debugInfo.enqRsTime
@@ -982,9 +981,6 @@ class RobImp(outer: Rob)(implicit p: Parameters) extends LazyModuleImp(outer)
       // we must make sure that skip is properly set to false (output from EXU is random value)
       difftest.io.skip     := RegNext(Mux(uop.eliminatedMove, false.B, exuOut.isMMIO || exuOut.isPerfCnt))
       difftest.io.isRVC    := RegNext(uop.cf.pd.isRVC)
-      difftest.io.scFailed := RegNext(!uop.diffTestDebugLrScValid &&
-        uop.ctrl.fuType === FuType.mou &&
-        (uop.ctrl.fuOpType === LSUOpType.sc_d || uop.ctrl.fuOpType === LSUOpType.sc_w))
       difftest.io.wen      := RegNext(io.commits.valid(i) && io.commits.info(i).rfWen && io.commits.info(i).ldest =/= 0.U)
       difftest.io.wpdest   := RegNext(io.commits.info(i).pdest)
       difftest.io.wdest    := RegNext(io.commits.info(i).ldest)

src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala

@@ -275,7 +275,6 @@ class AtomicsUnit(implicit p: Parameters) extends XSModule with MemoryOpConstant
     io.out.valid := true.B
     io.out.bits.uop := in.uop
     io.out.bits.uop.cf.exceptionVec := exceptionVec
-    io.out.bits.uop.diffTestDebugLrScValid := is_lrsc_valid
     io.out.bits.data := resp_data
     io.out.bits.redirectValid := false.B
     io.out.bits.redirect := DontCare
@@ -303,4 +302,14 @@ class AtomicsUnit(implicit p: Parameters) extends XSModule with MemoryOpConstant
     difftest.io.atomicFuop := fuop_reg
     difftest.io.atomicOut  := resp_data_wire
   }
+
+  if (env.EnableDifftest || env.AlwaysBasicDiff) {
+    val uop = io.out.bits.uop
+    val difftest = Module(new DifftestLrScEvent)
+    difftest.io.clock := clock
+    difftest.io.coreid := io.hartId
+    difftest.io.valid := io.out.fire &&
+      (uop.ctrl.fuOpType === LSUOpType.sc_d || uop.ctrl.fuOpType === LSUOpType.sc_w)
+    difftest.io.success := is_lrsc_valid
+  }
 }