trigger: fix lq hitvec raddr

08596256 · William Wang · fd9fd860 · 08596256
隐藏空白更改
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src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala +1 -1

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--- a/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
+++ b/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
@@ -741,7 +741,7 @@ class LoadQueue(implicit p: Parameters) extends XSModule
  })

  (0 until LoadPipelineWidth).map(i => {
-    vaddrTriggerResultModule.io.raddr(i) := loadWbSel(i)
+    vaddrTriggerResultModule.io.raddr(i) := loadWbSelGen(i)
    io.trigger(i).lqLoadAddrTriggerHitVec := vaddrTriggerResultModule.io.rdata(i)
  })