support cmo (#1360)

* pma: allow r/w priv for l3-cache op mmio space

* bump huancun

* bump huancun

* bump huancun

src/main/scala/xiangshan/backend/fu/PMA.scala

@@ -108,8 +108,8 @@ trait PMAMethod extends PMAConst {
       MemMap("h00_3801_0000", "h00_3801_FFFF",   "h0", "BEU",         "RW"),
       MemMap("h00_3802_0000", "h00_3802_0FFF",   "h0", "DebugModule", "RWX"),
       MemMap("h00_3802_1000", "h00_3802_1FFF",   "h0", "MMPMA",       "RW"),
-      MemMap("h00_3802_2000", "h00_3900_0FFF",   "h0", "Reserved",    ""),
-      MemMap("h00_3900_1000", "h00_3900_1FFF",   "h0", "Core_reset",  "RW"),
+      MemMap("h00_3802_2000", "h00_3900_0000",   "h0", "Reserved",    ""),
+      MemMap("h00_3900_0000", "h00_3900_1FFF",   "h0", "L3CacheCtrl",  "RW"),
       MemMap("h00_3900_2000", "h00_39FF_FFFF",   "h0", "Reserved",    ""),
       MemMap("h00_3A00_0000", "h00_3A00_0FFF",   "h0", "PLL0",        "RW),
       MemMap('h00_3A00_1000", "h00_3BFF_FFFF",   "h0", "Reserved",    ""),
@@ -166,7 +166,7 @@ trait PMAMethod extends PMAConst {
     cfg(idx).a := 1.U; cfg(idx).r := true.B; cfg(idx).w := true.B
     idx = idx - 1
 
-    addr(idx) := shift_addr(0x39001000)
+    addr(idx) := shift_addr(0x39000000)
     cfg(idx).a := 1.U
     idx = idx - 1
 
@@ -197,10 +197,9 @@ trait PMAMethod extends PMAConst {
     addr(idx) := shift_addr( 0x10000000)
     cfg(idx).a := 1.U; cfg(idx).r := true.B; cfg(idx).w := true.B
     idx = idx - 1
-
-    addr(idx) := shift_addr(0)
-
+    
     require(idx >= 0)
+    addr(idx) := shift_addr(0)
 
     val cfgInitMerge = cfg.asTypeOf(Vec(num/8, UInt(PMXLEN.W)))
     (cfgInitMerge, addr, mask)