Debug Mode: support difftest with spike (#1363)

* Debug Mode: support basic difftest with spike

* Debug Mode: fix some bugs

Bugs fixed are:
1. All interrupts and exceptions cause debug mode to enter park loop
2. Debug interrupt ignored due to flushPipe

difftest @ 95754bc8

-Subproject commit a541a4062292dc1e0d26e543fc932fce41305871
+Subproject commit 95754bc84e8a8c361a83a823d4efb69e2f7e8d6e

src/main/scala/top/Configs.scala

@@ -43,7 +43,7 @@ class BaseConfig(n: Int) extends Config((site, here, up) => {
   case DebugModuleKey => Some(XSDebugModuleParams(site(XLen)))
   case JtagDTMKey => JtagDTMKey
   case MaxHartIdBits => 2
-  case EnableJtag => false.B
+  case EnableJtag => true.B
 })
 
 // Synthesizable minimal XiangShan

src/main/scala/xiangshan/backend/fu/CSR.scala

@@ -823,7 +823,7 @@ class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst with PMP
   // Branch control
   val retTarget = Wire(UInt(VAddrBits.W))
   val resetSatp = addr === Satp.U && wen // write to satp will cause the pipeline be flushed
-  flushPipe := resetSatp || (valid && func === CSROpType.jmp && !isEcall)
+  flushPipe := resetSatp || (valid && func === CSROpType.jmp && !isEcall && !isEbreak)
 
   retTarget := DontCare
   // val illegalEret = TODO
@@ -943,8 +943,8 @@ class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst with PMP
 
   val raiseExceptionIntr = csrio.exception.valid
 
-  val raiseDebugExceptionIntr = !debugMode && hasbreakPoint || raiseDebugIntr || hasSingleStep || hasTriggerHit // todo
-  val ebreakEnterParkLoop = debugMode && raiseExceptionIntr // exception in debug mode (except ebrk) changes cmderr. how ???
+  val raiseDebugExceptionIntr = !debugMode && (hasbreakPoint || raiseDebugIntr || hasSingleStep || hasTriggerHit)
+  val ebreakEnterParkLoop = debugMode && hasbreakPoint
 
   XSDebug(raiseExceptionIntr, "int/exc: pc %x int (%d):%x exc: (%d):%x\n",
     csrio.exception.bits.uop.cf.pc, intrNO, intrVec, exceptionNO, raiseExceptionVec.asUInt
@@ -1113,6 +1113,9 @@ class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst with PMP
     difftest.io.intrNO := RegNext(RegNext(RegNext(difftestIntrNO)))
     difftest.io.cause  := RegNext(RegNext(RegNext(Mux(csrio.exception.valid, causeNO, 0.U))))
     difftest.io.exceptionPC := RegNext(RegNext(RegNext(SignExt(csrio.exception.bits.uop.cf.pc, XLEN))))
+    if (env.EnableDifftest) {
+      difftest.io.exceptionInst := RegNext(RegNext(RegNext(csrio.exception.bits.uop.cf.instr)))
+    }
   }
 
   // Always instantiate basic difftest modules.
@@ -1139,6 +1142,17 @@ class CSR(implicit p: Parameters) extends FunctionUnit with HasCSRConst with PMP
     difftest.io.mideleg := mideleg
     difftest.io.medeleg := medeleg
   }
+
+  if(env.AlwaysBasicDiff || env.EnableDifftest) {
+    val difftest = Module(new DifftestDebugMode)
+    difftest.io.clock := clock
+    difftest.io.coreid := csrio.hartId
+    difftest.io.debugMode := debugMode
+    difftest.io.dcsr := dcsr
+    difftest.io.dpc := dpc
+    difftest.io.dscratch0 := dscratch
+    difftest.io.dscratch1 := dscratch1
+  }
 }
 
 class PFEvent(implicit p: Parameters) extends XSModule with HasCSRConst  {

src/main/scala/xiangshan/backend/rename/Rename.scala

@@ -321,7 +321,7 @@ class Rename(implicit p: Parameters) extends XSModule with HasPerfEvents {
   val is_fused_lui_load = io.out.map(o => o.fire() && o.bits.ctrl.fuType === FuType.ldu && o.bits.ctrl.srcType(0) === SrcType.imm)
   XSPerfAccumulate("fused_lui_load_instr_count", PopCount(is_fused_lui_load))
 
-
+  
   val renamePerf = Seq(
     ("rename_in                  ", PopCount(io.in.map(_.valid & io.in(0).ready ))                                                               ),
     ("rename_waitinstr           ", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready))                                  ),