- 21 12月, 2021 1 次提交
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由 Yinan Xu 提交于
This commit adds an LsqEnqCtrl module to add one more clock cycle between dispatch and load/store queue. LsqEnqCtrl maintains the lqEnqPtr/sqEnqPtr and lqCounter/sqCounter. They are used to determine whether load/store queue can accept new instructions. After that, instructions are sent to load/store queue. This module decouples queue allocation and real enqueue. Besides, uop storage in load/store queue are optimized. In dispatch, only robIdx is required. Other information is naturally conveyed in the pipeline and can be stored later in load/store queue if needed. For example, exception vector, trigger, ftqIdx, pdest, etc are unnecessary before the instruction leaves the load/store pipeline.
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- 10 12月, 2021 1 次提交
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由 Yinan Xu 提交于
This commit optimizes the coding style and timing for hardware performance counters. By default, performance counters are RegNext(RegNext(_)).
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- 09 12月, 2021 1 次提交
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由 Yinan Xu 提交于
This commit adds WritebackSink and WritebackSource parameters for multiple modules. These traits hide implementation details from other modules by defining IO-related functions in modules. By using WritebackSink, ROB is able to choose the writeback sources. Now fflags and exceptions are connected from exe units to reduce write ports and optimize timing. Further optimizations on write-back to RS and better coding style to be added later.
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- 30 11月, 2021 1 次提交
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由 Yinan Xu 提交于
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- 16 11月, 2021 1 次提交
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由 Jiawei Lin 提交于
* FDivSqrt: use hierarchy API to avoid dedup bug * Dedup: use hartId from io port instead of core parameters * Bump fudian
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- 12 11月, 2021 1 次提交
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由 Yinan Xu 提交于
* difftest: add basic difftest features for releases This commit adds basic difftest features for every release, no matter it's for simulation or physical design. The macro SYNTHESIS is used to skip these logics when synthesizing the design. This commit aims at allowing designs for physical design to be verified. * bump ready-to-run * difftest: add int and fp writeback data
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- 11 11月, 2021 1 次提交
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由 Yinan Xu 提交于
* disable log as default * code clean up
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- 24 10月, 2021 1 次提交
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由 Yinan Xu 提交于
This commit changes when instructions enter load/store queue. Now, at dispatch2, load/store instructions enter load/store queue.
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- 23 10月, 2021 1 次提交
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由 rvcoresjw 提交于
* Add perf counters * add reg from hpm counter source * add print perfcounter enable
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- 18 10月, 2021 1 次提交
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由 Yinan Xu 提交于
Previously difftest uses the extra 32 read ports of regfile and it is disabled by default under FPGAPlatform. However, when FPGAPlatform is enabled, we also drop the right 32 read ports and it causes errors.
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- 16 10月, 2021 1 次提交
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由 Yinan Xu 提交于
This commit removes flush IO for every module. Flush now re-uses redirect ports to flush the instructions.
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- 12 10月, 2021 2 次提交
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由 Yinan Xu 提交于
This commit adds IOs for performance counters in reservation stations. Only `full` is included for now.
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由 William Wang 提交于
* mem: update block load logic Now load will be selected as soon as the store it depends on is ready, which is predicted by Store Sets * mem: opt block load logic Load blocked by std invalid will wait for that std to issue Load blocked by load violation wait for that sta to issue * csr: add 2 extra storeset config bits Following bits were added to slvpredctl: - storeset_wait_store - storeset_no_fast_wakeup * storeset: fix waitForSqIdx generate logic Now right waitForSqIdx will be generated for earlier store in the same dispatch bundle
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- 11 10月, 2021 1 次提交
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由 William Wang 提交于
Make bank conflict feedback 1 cycle earlier
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- 09 10月, 2021 1 次提交
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由 Yinan Xu 提交于
This commit adds fpStateReadOut and fpStateReadIn ports to Scheduler to support reading fp reg states from other schedulers. It should have better timing because now ExuBlock(0) has only int regfile and busytable. This block does not need fp writeback any more.
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- 01 10月, 2021 1 次提交
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由 Yinan Xu 提交于
This commit moves load/store reservation stations into the first ExuBlock (or calling it IntegerBlock). The unnecessary dispatch module is also removed from CtrlBlock. Now the module organization becomes: * ExuBlock: Int RS, Load/Store RS, Int RF, Int FUs * ExuBlock_1: Fp RS, Fp RF, Fp FUs * MemBlock: Load/Store FUs Besides, load queue has 80 entries and store queue has 64 entries now.
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- 28 9月, 2021 1 次提交
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由 Yinan Xu 提交于
* change ROB to 256 entries * change physical register file to 192 entries * re-organize reservation stations, function units and regfile
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- 20 9月, 2021 1 次提交
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由 Yinan Xu 提交于
This commit splits FMA instructions into FMUL and FADD for execution. When the first two operands are ready, an FMA instruction can be issued and the intermediate result will be written back to RS after two cycles. Since RS currently has DataArray to store the operands, we reuse it to store the intermediate FMUL result. When an FMA enters deq stage and leaves RS with only two operands, we mark it as midState ready at this clock cycle T0. If the instruction's third operand becomes ready at T0, it can be selected at T1 and issued at T2, when FMUL is also finished. The intermediate result will be sent to FADD instead of writing back to RS. If the instruction's third operand becomes ready later, we have the data in DataArray or at DataArray's write port. Thus, it's ok to set midState ready at clock cycle T0. The separation of FMA instructions will increase issue pressure since RS needs to issue more times. However, it larges reduce FMA latency if many FMA instructions are waiting for the third operand.
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- 19 9月, 2021 1 次提交
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由 Yinan Xu 提交于
This commit adds load balance strategy in issue selection logic for reservation stations. Previously we have a load balance option in ExuBlock, but it cannot work if the function units have feedbacks to RS. In this commit it is removed. This commit adds a victim index option for oldestFirst. For LOAD, the first issue port has better performance and thus we set the victim index to 0. For other function units, we use the last issue port.
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- 17 9月, 2021 1 次提交
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由 Yinan Xu 提交于
This commit adds manual reset for every register in Regfile. Previously the reset is done by add reset values to the registers. However, physically general-purpose register file does not have reset values. Since all the regfile always has the same writeback data, we don't need to explicitly assign reset data.
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- 02 9月, 2021 1 次提交
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由 Yinan Xu 提交于
This PR adds support for fast load-to-load wakeup and issue. In load-to-load fast wakeup and issue, load-to-load latency is reduced to 2 cycles. Now a load instruction can wakeup another load instruction at LOAD stage 1. When the producer load instruction arrives at stage 2, the consumer load instruction is issued to load stage 0 and using data from the producer to generate load address. In reservation station, load can be dequeued from staged 1 when stage 2 does not have a valid instruction. If the fast load is not accepted, from the next cycle on, the load will dequeue as normal. Timing in reservation station (for imm read) and load unit (for writeback data selection) to be optimized later. * backend,rs: issue load one cycle earlier when possible This commit adds support for issuing load instructions one cycle earlier if the load instruction is wakeup by another load. An extra 2-bit UInt is added to IO. * mem: add load to load addr fastpath framework * mem: enable load to load forward * mem: add load-load forward counter Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>
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- 25 8月, 2021 1 次提交
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由 Yinan Xu 提交于
* Refactor print control transform * Adda tilelink bus pmu * Add performance counters for dispatch, issue, execute stages * Add more counters in bus pmu * Insert BusPMU between L3 and L2 * add some TMA perfcnt Co-authored-by: NLinJiawei <linjiawei20s@ict.ac.cn> Co-authored-by: NWilliam Wang <zeweiwang@outlook.com> Co-authored-by: Nwangkaifan <wangkaifan@ict.ac.cn>
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- 22 8月, 2021 1 次提交
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由 Yinan Xu 提交于
This commit limits dequeue width of every RS to 2 for better timing.
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- 21 8月, 2021 1 次提交
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由 Yinan Xu 提交于
This commit separates store address and store data in backend, including both reservation stations and function units. This commit also changes how stIssuePtr is updated. stIssuePtr should only be updated when both store data and address issue.
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- 04 8月, 2021 1 次提交
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由 Yinan Xu 提交于
Backend --> ExuBlock --> FuBlock --> Exu --> Function Units --> --> Scheduler --> RS
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- 25 7月, 2021 1 次提交
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由 Yinan Xu 提交于
This commit adds support for multiple enqueue for load and store RS. Also update the parameters in XSCore to avoid explicitly setting wakeup ports.
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- 24 7月, 2021 1 次提交
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由 Yinan Xu 提交于
XiangShan is jointly released by ICT and PCL.
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- 17 7月, 2021 3 次提交
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由 Yinan Xu 提交于
* change the number of function units in MinimalConfig * remove some hard-wired values
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由 Yinan Xu 提交于
This commit adds support for a parameterized scheduler. A scheduler can be parameterized via issue and dispatch ports. Note: other parameters have not been tested.
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由 Yinan Xu 提交于
This commit adds an non-parameterized scheduler containing all reservation stations. Now IntegerBlock, FloatBlock, MemBlock contain only function units. The Schduler connects dispatch with all function units. Parameterization to be added later.
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- 16 7月, 2021 2 次提交
- 14 7月, 2021 1 次提交
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由 Yinan Xu 提交于
This commit adds an non-parameterized scheduler containing all reservation stations. Now IntegerBlock, FloatBlock, MemBlock contain only function units. The Schduler connects dispatch with all function units. Parameterization to be added later.
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