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    scheduler: fix regfile read ports connection (#1133) · fe58a36b
    Yinan Xu 提交于
    Previously difftest uses the extra 32 read ports of regfile and it is
    disabled by default under FPGAPlatform. However, when FPGAPlatform is
    enabled, we also drop the right 32 read ports and it causes errors.
    fe58a36b
Scheduler.scala 20.1 KB