scheduler: add support for parameterization via rs and dp ports (#882)

This commit adds support for a parameterized scheduler. A scheduler
can be parameterized via issue and dispatch ports.

Note: other parameters have not been tested.

src/main/scala/xiangshan/Parameters.scala

@@ -141,10 +141,8 @@ case class XSCoreParameters
   val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg)
   val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StExeUnitCfg)
 
-  val intExuConfigs = JumpExeUnitCfg +: (
-    Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) ++
-      Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg)
-    )
+  val intExuConfigs = Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++
+    Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpExeUnitCfg
 
   val fpExuConfigs =
     Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++
@@ -227,11 +225,11 @@ trait HasXSParameter {
   val StoreQueueSize = coreParams.StoreQueueSize
   val dpParams = coreParams.dpParams
   val exuParameters = coreParams.exuParameters
-  val NRIntReadPorts = coreParams.NRIntReadPorts
-  val NRIntWritePorts = coreParams.NRIntWritePorts
   val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt
-  val NRFpReadPorts = coreParams.NRFpReadPorts
-  val NRFpWritePorts = coreParams.NRFpWritePorts
+  val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts
+  val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt
+  val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt
+  val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt
   val LoadPipelineWidth = coreParams.LoadPipelineWidth
   val StorePipelineWidth = coreParams.StorePipelineWidth
   val StoreBufferSize = coreParams.StoreBufferSize

src/main/scala/xiangshan/XSCore.scala

@@ -21,12 +21,10 @@ import xiangshan.backend._
 import xiangshan.backend.fu.HasExceptionNO
 import xiangshan.backend.exu.Wb
 import xiangshan.frontend._
-import xiangshan.mem._
-import xiangshan.cache.{DCacheParameters, ICacheParameters, L1plusCacheWrapper, L1plusCacheParameters, PTWWrapper, PTWRepeater, PTWFilter}
-import xiangshan.cache.prefetch._
+import xiangshan.cache.{L1plusCacheWrapper, PTWWrapper, PTWRepeater, PTWFilter}
 import chipsalliance.rocketchip.config
 import chipsalliance.rocketchip.config.Parameters
-import freechips.rocketchip.diplomacy.{Description, LazyModule, LazyModuleImp, ResourceAnchors, ResourceBindings, SimpleDevice}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
 import freechips.rocketchip.tile.HasFPUParameters
 import system.{HasSoCParameter, L1CacheErrorInfo}
 import utils._
@@ -69,6 +67,45 @@ abstract class XSCoreBase()(implicit p: config.Parameters) extends LazyModule
   val ptw = LazyModule(new PTWWrapper())
   val memBlock = LazyModule(new MemBlock)
 
+  // TODO: better RS organization
+  // generate rs according to number of function units
+  require(exuParameters.JmpCnt == 1)
+  require(exuParameters.MduCnt <= exuParameters.AluCnt && exuParameters.MduCnt > 0)
+  require(exuParameters.FmiscCnt <= exuParameters.FmacCnt && exuParameters.FmiscCnt > 0)
+  require(exuParameters.LduCnt == 2 && exuParameters.StuCnt == 2)
+  // one RS every 2 MDUs
+  val schedulePorts = Seq(
+    // exuCfg, numDeq, intFastWakeupTarget, fpFastWakeupTarget
+    (AluExeUnitCfg, exuParameters.AluCnt, Seq(0, 1, 2, 5, 6, 7, 8), Seq()),
+    (MulDivExeUnitCfg, exuParameters.MduCnt, Seq(0, 1, 2, 5, 6, 7, 8), Seq()),
+    (JumpExeUnitCfg, 1, Seq(), Seq()),
+    (FmacExeUnitCfg, exuParameters.FmacCnt, Seq(), Seq(3, 4)),
+    (FmiscExeUnitCfg, exuParameters.FmiscCnt, Seq(), Seq(3, 4)),
+    (LdExeUnitCfg, 1, Seq(0, 5, 6), Seq()),
+    (LdExeUnitCfg, 1, Seq(0, 5, 6), Seq()),
+    (StExeUnitCfg, 1, Seq(), Seq()),
+    (StExeUnitCfg, 1, Seq(), Seq())
+  )
+  // allow mdu and fmisc to have 2*numDeq enqueue ports
+  val intDpPorts = (0 until exuParameters.AluCnt).map(i => {
+    if (i < exuParameters.JmpCnt) Seq((0, i), (1, i), (2, i))
+    else if (i < 2*exuParameters.MduCnt) Seq((0, i), (1, i))
+    else Seq((0, i))
+  })
+  val fpDpPorts = (0 until exuParameters.FmacCnt).map(i => {
+    if (i < 2*exuParameters.FmiscCnt) Seq((3, i), (4, i))
+    else Seq((4, i))
+  })
+  val lsDpPorts = Seq(
+    Seq((5, 0)),
+    Seq((6, 0)),
+    Seq((7, 0)),
+    Seq((8, 0))
+  )
+  val dispatchPorts = intDpPorts ++ fpDpPorts ++ lsDpPorts
+
+  val scheduler = LazyModule(new Scheduler(schedulePorts, dispatchPorts))
+
 }
 
 class XSCore()(implicit p: config.Parameters) extends XSCoreBase
@@ -97,7 +134,7 @@ class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer)
   val intBlockSlowWakeUp = intExuConfigs.filter(_.hasUncertainlatency)
 
   val ctrlBlock = Module(new CtrlBlock)
-  val scheduler = Module(new Scheduler)
+
   val integerBlock = Module(new IntegerBlock)
   val floatBlock = Module(new FloatBlock)
 
@@ -105,10 +142,12 @@ class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer)
   val memBlock = outer.memBlock.module
   val l1pluscache = outer.l1pluscache.module
   val ptw = outer.ptw.module
+  val scheduler = outer.scheduler.module
 
-  val intConfigs = intExuConfigs ++ fpExuConfigs.filter(_.writeIntRf) ++ loadExuConfigs
+  val allWriteback = integerBlock.io.writeback ++ floatBlock.io.writeback ++ memBlock.io.writeback
+  val intConfigs = exuConfigs.filter(_.writeIntRf)
   val intArbiter = Module(new Wb(intConfigs, NRIntWritePorts, isFp = false))
-  val intWriteback = integerBlock.io.writeback ++ floatBlock.io.writeback.drop(4) ++ memBlock.io.writeback.take(2)
+  val intWriteback = allWriteback.zip(exuConfigs).filter(_._2.writeIntRf).map(_._1)
   // set default value for ready
   integerBlock.io.writeback.map(_.ready := true.B)
   floatBlock.io.writeback.map(_.ready := true.B)
@@ -121,12 +160,8 @@ class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer)
     }
   }
 
-  val fpArbiter = Module(new Wb(
-    fpExuConfigs ++ intExuConfigs.take(1) ++ loadExuConfigs,
-    NRFpWritePorts,
-    isFp = true
-  ))
-  val fpWriteback = floatBlock.io.writeback ++ integerBlock.io.writeback.take(1) ++ memBlock.io.writeback.take(2)
+  val fpArbiter = Module(new Wb(exuConfigs.filter(_.writeFpRf), NRFpWritePorts, isFp = true))
+  val fpWriteback = allWriteback.zip(exuConfigs).filter(_._2.writeFpRf).map(_._1)
   fpArbiter.io.in.zip(fpWriteback).foreach{ case (arb, wb) =>
     arb.valid := wb.valid && wb.bits.uop.ctrl.fpWen
     arb.bits := wb.bits

src/main/scala/xiangshan/backend/CtrlBlock.scala

@@ -183,7 +183,7 @@ class CtrlBlock(implicit p: Parameters) extends XSModule
   with HasCircularQueuePtrHelper with HasFtqHelper {
   val io = IO(new Bundle {
     val frontend = Flipped(new FrontendToBackendIO)
-    val enqIQ = Vec(12, DecoupledIO(new MicroOp))
+    val enqIQ = Vec(exuParameters.CriticalExuCnt, DecoupledIO(new MicroOp))
     // from int block
     val exuRedirect = Vec(exuParameters.AluCnt + exuParameters.JmpCnt, Flipped(ValidIO(new ExuOutput)))
     val stIn = Vec(exuParameters.StuCnt, Flipped(ValidIO(new ExuInput)))
@@ -343,7 +343,7 @@ class CtrlBlock(implicit p: Parameters) extends XSModule
     fpBusyTable.io.allocPregs(i).bits := preg.preg
   }
   dispatch.io.enqIQCtrl := DontCare
-  io.enqIQ <> dispatch.io.enqIQCtrl.take(4) ++ dispatch.io.enqIQCtrl.slice(7, 11) ++ dispatch.io.enqIQCtrl.drop(13)
+  io.enqIQ <> dispatch.io.enqIQCtrl
   dispatch.io.csrCtrl <> io.csrCtrl
   dispatch.io.storeIssue <> io.stIn
   dispatch.io.readIntRf <> io.readIntRf

src/main/scala/xiangshan/backend/FloatBlock.scala

@@ -31,44 +31,13 @@ class FloatBlock()(implicit p: Parameters) extends XSModule with HasExeBlockHelp
     val redirect = Flipped(ValidIO(new Redirect))
     val flush = Input(Bool())
     // in
-    val issue = Vec(6, Flipped(DecoupledIO(new ExuInput)))
+    val issue = Vec(exuParameters.FpExuCnt, Flipped(DecoupledIO(new ExuInput)))
     // out
-    val writeback = Vec(6, DecoupledIO(new ExuOutput))
+    val writeback = Vec(exuParameters.FpExuCnt, DecoupledIO(new ExuOutput))
     // misc from csr
     val frm = Input(UInt(3.W))
   })
 
-//  val intWakeUpFpReg = Wire(Vec(intSlowWakeUpIn.size, Flipped(DecoupledIO(new ExuOutput))))
-//  for((w, r) <- io.intWakeUpFp.zip(intWakeUpFpReg)){
-//    val in = WireInit(w)
-//    w.ready := in.ready
-//    in.valid := w.valid && !w.bits.uop.roqIdx.needFlush(io.redirect, io.flush)
-//    PipelineConnect(in, r, r.fire() || r.bits.uop.roqIdx.needFlush(io.redirect, io.flush), false.B)
-//  }
-//  // to memBlock's store rs
-//  io.intWakeUpOut <> intWakeUpFpReg.map(x => WireInit(x))
-//
-//  val intRecoded = intWakeUpFpReg.map(x => {
-//    val rec = Wire(DecoupledIO(new ExuOutput))
-//    rec.valid := x.valid && x.bits.uop.ctrl.fpWen
-//    rec.bits := x.bits
-//    rec.bits.data := Mux(x.bits.uop.ctrl.fpu.typeTagOut === S,
-//      recode(x.bits.data(31, 0), S),
-//      recode(x.bits.data(63, 0), D)
-//    )
-//    rec.bits.redirectValid := false.B
-//    x.ready := rec.ready || !rec.valid
-//    rec
-//  })
-
-//  val memRecoded = WireInit(io.memWakeUpFp)
-//  for((rec, reg) <- memRecoded.zip(io.memWakeUpFp)){
-//    rec.bits.data := fpRdataHelper(reg.bits.uop, reg.bits.data)
-//    rec.bits.redirectValid := false.B
-//    reg.ready := true.B
-//  }
-//  val wakeUpInRecode = intRecoded ++ memRecoded
-
   val fmacExeUnits = Array.tabulate(exuParameters.FmacCnt)(_ => Module(new FmacExeUnit))
   val fmiscExeUnits = Array.tabulate(exuParameters.FmiscCnt)(_ => Module(new FmiscExeUnit))
 
@@ -83,6 +52,7 @@ class FloatBlock()(implicit p: Parameters) extends XSModule with HasExeBlockHelp
 
     // in
     exeUnits(i).io.fromFp <> io.issue(i)
+    // fp instructions have three operands
     for (j <- 0 until 3) {
       // when one of the higher bits is zero, then it's not a legal single-precision number
       val isLegalSingle = io.issue(i).bits.uop.ctrl.fpu.typeTagIn === S && io.issue(i).bits.src(j)(63, 32).andR

src/main/scala/xiangshan/backend/IntegerBlock.scala

@@ -89,10 +89,10 @@ class IntegerBlock()(implicit p: Parameters) extends XSModule with HasExeBlockHe
     val redirect = Flipped(ValidIO(new Redirect))
     val flush = Input(Bool())
     // in
-    val issue = Vec(7, Flipped(DecoupledIO(new ExuInput)))
+    val issue = Vec(exuParameters.IntExuCnt, Flipped(DecoupledIO(new ExuInput)))
     // out
     val exuRedirect = Vec(exuParameters.AluCnt + exuParameters.JmpCnt, ValidIO(new ExuOutput))
-    val writeback = Vec(7, DecoupledIO(new ExuOutput))
+    val writeback = Vec(exuParameters.IntExuCnt, DecoupledIO(new ExuOutput))
     // misc
     val csrio = new CSRFileIO
     val fenceio = new Bundle {
@@ -101,12 +101,11 @@ class IntegerBlock()(implicit p: Parameters) extends XSModule with HasExeBlockHe
       val sbuffer = new FenceToSbuffer // to mem
     }
   })
-
-  val jmpExeUnit = Module(new JumpExeUnit)
-  val mduExeUnits = Array.tabulate(exuParameters.MduCnt)(_ => Module(new MulDivExeUnit))
   val aluExeUnits = Array.tabulate(exuParameters.AluCnt)(_ => Module(new AluExeUnit))
+  val mduExeUnits = Array.tabulate(exuParameters.MduCnt)(_ => Module(new MulDivExeUnit))
+  val jmpExeUnit = Module(new JumpExeUnit)
 
-  val exeUnits = jmpExeUnit +: (mduExeUnits ++ aluExeUnits)
+  val exeUnits = aluExeUnits ++ mduExeUnits :+ jmpExeUnit
   io.writeback <> exeUnits.map(_.io.out)
 
   for ((exe, i) <- exeUnits.zipWithIndex) {
@@ -117,7 +116,7 @@ class IntegerBlock()(implicit p: Parameters) extends XSModule with HasExeBlockHe
 
   // send misprediction to brq
   io.exuRedirect.zip(
-    exeUnits.filter(_.config.hasRedirect).map(_.io.out)
+    (jmpExeUnit +: aluExeUnits).map(_.io.out)
   ).foreach {
     case (x, y) =>
       x.valid := y.fire() && y.bits.redirectValid

src/main/scala/xiangshan/backend/MemBlock.scala

@@ -48,15 +48,15 @@ class MemBlockImp(outer: MemBlock) extends LazyModuleImp(outer)
     val redirect = Flipped(ValidIO(new Redirect))
     val flush = Input(Bool())
     // in
-    val issue = Vec(4, Flipped(DecoupledIO(new ExuInput)))
-    val replay = Vec(4, ValidIO(new RSFeedback))
-    val rsIdx = Vec(4, Input(UInt(log2Up(IssQueSize).W)))
-    val isFirstIssue = Vec(4, Input(Bool()))
-    val stData = Vec(2, Flipped(ValidIO(new StoreDataBundle)))
+    val issue = Vec(exuParameters.LsExuCnt, Flipped(DecoupledIO(new ExuInput)))
+    val replay = Vec(exuParameters.LsExuCnt, ValidIO(new RSFeedback))
+    val rsIdx = Vec(exuParameters.LsExuCnt, Input(UInt(log2Up(IssQueSize).W)))
+    val isFirstIssue = Vec(exuParameters.LsExuCnt, Input(Bool()))
+    val stData = Vec(exuParameters.StuCnt, Flipped(ValidIO(new StoreDataBundle)))
     val stIssuePtr = Output(new SqPtr())
     // out
-    val writeback = Vec(4, DecoupledIO(new ExuOutput))
-    val otherFastWakeup = Vec(2, ValidIO(new MicroOp))
+    val writeback = Vec(exuParameters.LsExuCnt, DecoupledIO(new ExuOutput))
+    val otherFastWakeup = Vec(exuParameters.LduCnt, ValidIO(new MicroOp))
     // misc
     val stIn = Vec(exuParameters.StuCnt, ValidIO(new ExuInput))
     val stOut = Vec(exuParameters.StuCnt, ValidIO(new ExuOutput))

src/main/scala/xiangshan/backend/dispatch/Dispatch.scala

@@ -57,13 +57,8 @@ class Dispatch(implicit p: Parameters) extends XSModule {
     val readIntState= Vec(NRIntReadPorts, Flipped(new BusyTableReadIO))
     val readFpState = Vec(NRFpReadPorts, Flipped(new BusyTableReadIO))
     // to reservation stations
-    val enqIQCtrl = Vec(exuParameters.ExuCnt, DecoupledIO(new MicroOp))
+    val enqIQCtrl = Vec(exuParameters.CriticalExuCnt, DecoupledIO(new MicroOp))
     // send reg file read port index to reservation stations
-    val readPortIndex = new Bundle {
-      val intIndex = Vec(exuParameters.IntExuCnt, Output(UInt(log2Ceil(8 / 2).W)))
-      val fpIndex = Vec(exuParameters.FpExuCnt, Output(UInt(log2Ceil((NRFpReadPorts - exuParameters.StuCnt) / 3).W)))
-      // ls: hardwired to (0, 1, 2, 4)
-    }
     val csrCtrl = Input(new CustomCSRCtrlIO)
     // LFST state sync
     val storeIssue = Vec(StorePipelineWidth, Flipped(Valid(new ExuInput)))
@@ -114,30 +109,20 @@ class Dispatch(implicit p: Parameters) extends XSModule {
   // Int dispatch queue to Int reservation stations
   val intDispatch = Module(new Dispatch2Int)
   intDispatch.io.fromDq <> intDq.io.deq
-  intDispatch.io.readRf.zipWithIndex.map({case (r, i) => r <> io.readIntRf(i)})
-  intDispatch.io.readState.zipWithIndex.map({case (r, i) => r <> io.readIntState(i)})
-  intDispatch.io.enqIQCtrl.zipWithIndex.map({case (enq, i) => enq <> io.enqIQCtrl(i)})
-//  intDispatch.io.enqIQData.zipWithIndex.map({case (enq, i) => enq <> io.enqIQData(i)})
-  intDispatch.io.readPortIndex <> io.readPortIndex.intIndex
 
   // Fp dispatch queue to Fp reservation stations
   val fpDispatch = Module(new Dispatch2Fp)
   fpDispatch.io.fromDq <> fpDq.io.deq
-  fpDispatch.io.readRf.zipWithIndex.map({case (r, i) => r <> io.readFpRf(i)})
-  fpDispatch.io.readState.zipWithIndex.map({case (r, i) => r <> io.readFpState(i)})
-  fpDispatch.io.enqIQCtrl.zipWithIndex.map({case (enq, i) => enq <> io.enqIQCtrl(i + exuParameters.IntExuCnt)})
-//  fpDispatch.io.enqIQData.zipWithIndex.map({case (enq, i) => enq <> io.enqIQData(i + exuParameters.IntExuCnt)})
-  fpDispatch.io.readPortIndex <> io.readPortIndex.fpIndex
-  
+
   // Load/store dispatch queue to load/store issue queues
   val lsDispatch = Module(new Dispatch2Ls)
   lsDispatch.io.fromDq <> lsDq.io.deq
-  lsDispatch.io.readIntRf.zipWithIndex.map({case (r, i) => r <> io.readIntRf(i + 8)})
-  lsDispatch.io.readFpRf.zipWithIndex.map({case (r, i) => r <> io.readFpRf(i + 12)})
-  lsDispatch.io.readIntState.zipWithIndex.map({case (r, i) => r <> io.readIntState(i + 8)})
-  lsDispatch.io.readFpState.zipWithIndex.map({case (r, i) => r <> io.readFpState(i + 12)})
-  lsDispatch.io.enqIQCtrl.zipWithIndex.map({case (enq, i) => enq <> io.enqIQCtrl(exuParameters.IntExuCnt + exuParameters.FpExuCnt + i)})
-//  lsDispatch.io.enqIQData.zipWithIndex.map({case (enq, i) => enq <> io.enqIQData(exuParameters.IntExuCnt + exuParameters.FpExuCnt + i)})
+
+  io.enqIQCtrl <> intDispatch.io.enqIQCtrl ++ fpDispatch.io.enqIQCtrl ++ lsDispatch.io.enqIQCtrl
+  io.readIntRf <> intDispatch.io.readRf ++ lsDispatch.io.readIntRf
+  io.readIntState <> intDispatch.io.readState ++ lsDispatch.io.readIntState
+  io.readFpRf <> fpDispatch.io.readRf ++ lsDispatch.io.readFpRf
+  io.readFpState <> fpDispatch.io.readState ++ lsDispatch.io.readFpState
 
   io.ctrlInfo <> DontCare
   io.ctrlInfo.intdqFull := intDq.io.dqFull

src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala

@@ -27,64 +27,18 @@ class Dispatch2Fp(implicit p: Parameters) extends XSModule {
     val fromDq = Flipped(Vec(dpParams.FpDqDeqWidth, DecoupledIO(new MicroOp)))
     val readRf = Vec(NRFpReadPorts - exuParameters.StuCnt, Output(UInt(PhyRegIdxWidth.W)))
     val readState = Vec(NRFpReadPorts - exuParameters.StuCnt, Flipped(new BusyTableReadIO))
-    val enqIQCtrl = Vec(exuParameters.FpExuCnt, DecoupledIO(new MicroOp))
-    val readPortIndex = Vec(exuParameters.FpExuCnt, Output(UInt(log2Ceil((NRFpReadPorts - exuParameters.StuCnt) / 3).W)))
+    val enqIQCtrl = Vec(exuParameters.FmacCnt, DecoupledIO(new MicroOp))
   })
 
-  io.enqIQCtrl <> DontCare
-  io.fromDq <> io.enqIQCtrl.take(4)
-  io.enqIQCtrl(4).valid := false.B
-  io.enqIQCtrl(5).valid := false.B
+  require(exuParameters.FmacCnt <= dpParams.FpDqDeqWidth)
 
-  for (i <- 0 until 4) {
+  io.enqIQCtrl <> DontCare
+  for (i <- 0 until exuParameters.FmacCnt) {
+    io.enqIQCtrl(i) <> io.fromDq(i)
     io.readRf(3*i) := io.enqIQCtrl(i).bits.psrc(0)
     io.readRf(3*i+1) := io.enqIQCtrl(i).bits.psrc(1)
     io.readRf(3*i+2) := io.enqIQCtrl(i).bits.psrc(2)
-  }
-
-  /**
-    * Part 1: generate indexes for reservation stations
-    */
-  // val fmacIndexGen = Module(new IndexMapping(dpParams.FpDqDeqWidth, exuParameters.FmacCnt, true))
-//  val fmacCanAccept = VecInit(io.fromDq.map(deq => deq.valid && FuType.fmacCanAccept(deq.bits.ctrl.fuType)))
-//  val (fmacPriority, fmacIndex) = PriorityGen((0 until exuParameters.FmacCnt).map(i => 0.U))
-  // fmacIndexGen.io.validBits := fmacCanAccept
-  // fmacIndexGen.io.priority := fmacPriority
-
-//  val fmiscIndexGen = Module(new IndexMapping(dpParams.FpDqDeqWidth, exuParameters.FmiscCnt, true))
-//  val fmiscCanAccept = VecInit(io.fromDq.map(deq => deq.valid && FuType.fmiscCanAccept(deq.bits.ctrl.fuType)))
-//  val (fmiscPriority, _) = PriorityGen((0 until exuParameters.FmiscCnt).map(i => 0.U))
-//  fmiscIndexGen.io.validBits := fmiscCanAccept
-//  fmiscIndexGen.io.priority := fmiscPriority
 
-  // val allIndexGen = Seq(fmacIndexGen, fmiscIndexGen)
-  // val validVec = allIndexGen.map(_.io.mapping.map(_.valid)).reduceLeft(_ ++ _)
-  // val indexVec = allIndexGen.map(_.io.mapping.map(_.bits)).reduceLeft(_ ++ _)
-  // for (i <- validVec.indices) {
-    // XSDebug(p"mapping $i: valid ${validVec(i)} index ${indexVec(i)}\n")
-  // }
-
-  /**
-    * Part 2: assign regfile read ports
-    */
-  // val fpStaticIndex = Seq(0, 1, 2, 3)
-  // val fpDynamicIndex = Seq(4, 5)
-  // val fpStaticMappedValid = fpStaticIndex.map(i => validVec(i))
-  // val fpDynamicMappedValid = fpDynamicIndex.map(i => validVec(i))
-  // val (fpReadPortSrc, fpDynamicExuSrc) = RegfileReadPortGen(fpStaticMappedValid, fpDynamicMappedValid)
-  // val fpStaticMapped = fpStaticIndex.map(i => indexVec(i))
-  // val fpDynamicMapped = fpDynamicIndex.map(i => indexVec(i))
-  // for (i <- fpStaticIndex.indices) {
-  //   val index = WireInit(VecInit(fpStaticMapped(i) +: fpDynamicMapped))
-  //   io.readRf(3*i  ) := io.fromDq(index(fpReadPortSrc(i))).bits.psrc(0)
-  //   io.readRf(3*i+1) := io.fromDq(index(fpReadPortSrc(i))).bits.psrc(1)
-  //   io.readRf(3*i+2) := io.fromDq(index(fpReadPortSrc(i))).bits.psrc(2)
-  // }
-  // val readPortIndex = Wire(Vec(exuParameters.FpExuCnt, UInt(2.W)))
-  // fpStaticIndex.zipWithIndex.map({case (index, i) => readPortIndex(index) := i.U})
-  // fpDynamicIndex.zipWithIndex.map({case (index, i) => readPortIndex(index) := fpDynamicExuSrc(i)})
-
-  for (i <- 0 until dpParams.IntDqDeqWidth) {
     io.readState(3*i  ).req := io.fromDq(i).bits.psrc(0)
     io.readState(3*i+1).req := io.fromDq(i).bits.psrc(1)
     io.readState(3*i+2).req := io.fromDq(i).bits.psrc(2)
@@ -92,112 +46,10 @@ class Dispatch2Fp(implicit p: Parameters) extends XSModule {
     io.enqIQCtrl(i).bits.srcState(1) := io.readState(3*i+1).resp
     io.enqIQCtrl(i).bits.srcState(2) := io.readState(3*i+2).resp
   }
-//  io.readRf(0)  := io.enqIQCtrl(0).bits.psrc(0)
-//  io.readRf(1)  := io.enqIQCtrl(0).bits.psrc(1)
-//  io.readRf(2)  := io.enqIQCtrl(0).bits.psrc(2)
-//  io.readRf(3)  := io.enqIQCtrl(1).bits.psrc(0)
-//  io.readRf(4)  := io.enqIQCtrl(1).bits.psrc(1)
-//  io.readRf(5)  := io.enqIQCtrl(1).bits.psrc(2)
-//  io.readRf(6)  := Mux(io.enqIQCtrl(2).valid, io.enqIQCtrl(2).bits.psrc(0), io.enqIQCtrl(4).bits.psrc(0))
-//  io.readRf(7)  := Mux(io.enqIQCtrl(2).valid, io.enqIQCtrl(2).bits.psrc(1), io.enqIQCtrl(4).bits.psrc(1))
-//  io.readRf(8)  := Mux(io.enqIQCtrl(2).valid, io.enqIQCtrl(2).bits.psrc(2), io.enqIQCtrl(4).bits.psrc(2))
-//  io.readRf(9)  := Mux(io.enqIQCtrl(3).valid, io.enqIQCtrl(3).bits.psrc(0), io.enqIQCtrl(5).bits.psrc(0))
-//  io.readRf(10) := Mux(io.enqIQCtrl(3).valid, io.enqIQCtrl(3).bits.psrc(1), io.enqIQCtrl(5).bits.psrc(1))
-//  io.readRf(11) := Mux(io.enqIQCtrl(3).valid, io.enqIQCtrl(3).bits.psrc(2), io.enqIQCtrl(5).bits.psrc(2))
 
-  /**
-    * Part 3: dispatch to reservation stations
-    */
-  // val fmacReady = Cat(io.enqIQCtrl.take(exuParameters.FmacCnt).map(_.ready)).andR
-//  val fmiscReady = Cat(io.enqIQCtrl.drop(exuParameters.FmacCnt).map(_.ready)).andR
-//  for (i <- 0 until exuParameters.FpExuCnt) {
-//    val enq = io.enqIQCtrl(i)
-//    val deqIndex = if (i < exuParameters.FmacCnt) fmacPriority(i) else fmiscIndexGen.io.mapping(i-exuParameters.FmacCnt).bits
-//    if (i < exuParameters.FmacCnt) {
-//      enq.valid := fmacCanAccept(fmacPriority(i))//fmacIndexGen.io.mapping(i).valid && fmacReady
-//    }
-//    else {
-//      enq.valid := fmiscIndexGen.io.mapping(i - exuParameters.FmacCnt).valid && fmiscReady && !io.enqIQCtrl(2).valid && !io.enqIQCtrl(3).valid
-//    }
-//    enq.bits := io.fromDq(deqIndex).bits
-//
-//    val src1Ready = VecInit((0 until 4).map(i => io.readState(i * 3).resp))
-//    val src2Ready = VecInit((0 until 4).map(i => io.readState(i * 3 + 1).resp))
-//    val src3Ready = VecInit((0 until 4).map(i => io.readState(i * 3 + 2).resp))
-//    enq.bits.srcState(0) := src1Ready(deqIndex)
-//    enq.bits.srcState(1) := src2Ready(deqIndex)
-//    enq.bits.srcState(2) := src3Ready(deqIndex)
-//
-//    XSInfo(enq.fire(), p"pc 0x${Hexadecimal(enq.bits.cf.pc)} with type ${enq.bits.ctrl.fuType} " +
-//      p"srcState(${enq.bits.srcState(0)} ${enq.bits.srcState(1)} ${enq.bits.srcState(2)}) " +
-//      p"enters reservation station $i from ${deqIndex}\n")
-//  }
+  for (i <- exuParameters.FmacCnt until dpParams.FpDqDeqWidth) {
+    io.fromDq(i).ready := false.B
+  }
 
-  /**
-    * Part 4: response to dispatch queue
-    */
-//  val fmisc2CanOut = !(fmiscCanAccept(0) && fmiscCanAccept(1))
-//  val fmisc3CanOut = !(fmiscCanAccept(0) && fmiscCanAccept(1) || fmiscCanAccept(0) && fmiscCanAccept(2) || fmiscCanAccept(1) && fmiscCanAccept(2))
-//  val fmacReadyVec = VecInit(io.enqIQCtrl.take(4).map(_.ready))
-//  for (i <- 0 until dpParams.FpDqDeqWidth) {
-//    io.fromDq(i).ready := fmacCanAccept(i) && fmacReadyVec(fmacIndex(i)) ||
-//                          fmiscCanAccept(i) && (if (i <= 1) true.B else if (i == 2) fmisc2CanOut else fmisc3CanOut) && fmiscReady && !io.enqIQCtrl(2).valid && !io.enqIQCtrl(3).valid
-//
-//    XSInfo(io.fromDq(i).fire(),
-//      p"pc 0x${Hexadecimal(io.fromDq(i).bits.cf.pc)} leaves Fp dispatch queue $i with nroq ${io.fromDq(i).bits.roqIdx}\n")
-//    XSDebug(io.fromDq(i).valid && !io.fromDq(i).ready,
-//      p"pc 0x${Hexadecimal(io.fromDq(i).bits.cf.pc)} waits at Fp dispatch queue with index $i\n")
-//  }
   XSError(PopCount(io.fromDq.map(_.fire())) =/= PopCount(io.enqIQCtrl.map(_.fire())), "deq =/= enq\n")
-
-  /**
-    * Part 5: send read port index of register file to reservation station
-    */
-  // io.readPortIndex := readPortIndex
-  io.readPortIndex := DontCare
-//  val readPortIndexReg = Reg(Vec(exuParameters.FpExuCnt, UInt(log2Ceil(NRFpReadPorts - exuParameters.StuCnt).W)))
-//  val uopReg = Reg(Vec(exuParameters.FpExuCnt, new MicroOp))
-//  val dataValidRegDebug = Reg(Vec(exuParameters.FpExuCnt, Bool()))
-//  for (i <- 0 until exuParameters.FpExuCnt) {
-//    readPortIndexReg(i) := readPortIndex(i)
-//    uopReg(i) := io.enqIQCtrl(i).bits
-//    dataValidRegDebug(i) := io.enqIQCtrl(i).fire()
-//
-//    io.enqIQData(i) := DontCare
-//    io.enqIQData(i).src(0) := io.readRf(readPortIndexReg(i)).data
-//    io.enqIQData(i).src(1) := io.readRf(readPortIndexReg(i) + 1.U).data
-//    io.enqIQData(i).src(2) := io.readRf(readPortIndexReg(i) + 2.U).data
-//
-//    XSDebug(dataValidRegDebug(i),
-//      p"pc 0x${Hexadecimal(uopReg(i).cf.pc)} reads operands from " +
-//        p"(${readPortIndexReg(i)    }, ${uopReg(i).psrc(0)}, ${Hexadecimal(io.enqIQData(i).src(0))}), " +
-//        p"(${readPortIndexReg(i)+1.U}, ${uopReg(i).psrc(1)}, ${Hexadecimal(io.enqIQData(i).src(1))}), " +
-//        p"(${readPortIndexReg(i)+2.U}, ${uopReg(i).psrc(2)}, ${Hexadecimal(io.enqIQData(i).src(2))})\n")
-//  }
-
-//  XSPerfAccumulate("in", PopCount(io.fromDq.map(_.valid)))
-//  XSPerfAccumulate("out", PopCount(io.enqIQCtrl.map(_.fire())))
-//  XSPerfAccumulate("out_fmac0", io.enqIQCtrl(0).fire())
-//  XSPerfAccumulate("out_fmac1", io.enqIQCtrl(1).fire())
-//  XSPerfAccumulate("out_fmac2", io.enqIQCtrl(2).fire())
-//  XSPerfAccumulate("out_fmac3", io.enqIQCtrl(3).fire())
-//  XSPerfAccumulate("out_fmisc0", io.enqIQCtrl(4).fire())
-//  XSPerfAccumulate("out_fmisc1", io.enqIQCtrl(5).fire())
-//  val block_num = PopCount(io.fromDq.map(deq => deq.valid && !deq.ready))
-//  XSPerfAccumulate("blocked", block_num)
-//  XSPerfAccumulate("blocked_index", Mux(block_num =/= 0.U, PriorityEncoder(io.fromDq.map(deq => deq.valid && !deq.ready)), 0.U))
-//  XSPerfAccumulate("misc_deq", PopCount(fmiscCanAccept))
-//  XSPerfAccumulate("misc_deq_exceed_limit", Mux(PopCount(fmiscCanAccept) >= 2.U, PopCount(fmiscCanAccept) - 2.U, 0.U))
-//  XSPerfAccumulate("mac0_blocked_by_mac0", io.enqIQCtrl(0).valid && !io.enqIQCtrl(0).ready)
-//  XSPerfAccumulate("mac1_blocked_by_mac1", io.enqIQCtrl(1).valid && !io.enqIQCtrl(1).ready)
-//  XSPerfAccumulate("mac2_blocked_by_mac2", io.enqIQCtrl(2).valid && !io.enqIQCtrl(2).ready)
-//  XSPerfAccumulate("mac3_blocked_by_mac3", io.enqIQCtrl(3).valid && !io.enqIQCtrl(3).ready)
-//  XSPerfAccumulate("misc0_blocked_by_mac", fmiscIndexGen.io.mapping(0).valid && fmiscReady && (io.enqIQCtrl(2).valid || io.enqIQCtrl(3).valid))
-//  XSPerfAccumulate("misc0_blocked_by_mac2", fmiscIndexGen.io.mapping(0).valid && fmiscReady && io.enqIQCtrl(2).valid && !io.enqIQCtrl(3).valid)
-//  XSPerfAccumulate("misc0_blocked_by_mac3", fmiscIndexGen.io.mapping(0).valid && fmiscReady && !io.enqIQCtrl(2).valid && io.enqIQCtrl(3).valid)
-//  XSPerfAccumulate("misc0_blocked_by_misc1", fmiscIndexGen.io.mapping(0).valid && io.enqIQCtrl(4).ready && !io.enqIQCtrl(5).ready && !io.enqIQCtrl(2).valid && !io.enqIQCtrl(3).valid)
-//  XSPerfAccumulate("misc1_blocked_by_mac", fmiscIndexGen.io.mapping(1).valid && fmiscReady && (io.enqIQCtrl(2).valid || io.enqIQCtrl(3).valid))
-//  XSPerfAccumulate("misc1_blocked_by_mac2", fmiscIndexGen.io.mapping(1).valid && fmiscReady && io.enqIQCtrl(2).valid && !io.enqIQCtrl(3).valid)
-//  XSPerfAccumulate("misc1_blocked_by_mac3", fmiscIndexGen.io.mapping(1).valid && fmiscReady && !io.enqIQCtrl(2).valid && io.enqIQCtrl(3).valid)
-//  XSPerfAccumulate("misc1_blocked_by_misc0", fmiscIndexGen.io.mapping(1).valid && !io.enqIQCtrl(4).ready && io.enqIQCtrl(5).ready && !io.enqIQCtrl(2).valid && !io.enqIQCtrl(3).valid)
 }

src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala

@@ -27,190 +27,26 @@ class Dispatch2Int(implicit p: Parameters) extends XSModule {
     val fromDq = Flipped(Vec(dpParams.IntDqDeqWidth, DecoupledIO(new MicroOp)))
     val readRf = Vec(NRIntReadPorts - NRMemReadPorts, Output(UInt(PhyRegIdxWidth.W)))
     val readState = Vec(NRIntReadPorts - NRMemReadPorts, Flipped(new BusyTableReadIO))
-    val enqIQCtrl = Vec(exuParameters.IntExuCnt, DecoupledIO(new MicroOp))
-    val readPortIndex = Vec(exuParameters.IntExuCnt, Output(UInt(log2Ceil(8 / 2).W)))
+    val enqIQCtrl = Vec(exuParameters.AluCnt, DecoupledIO(new MicroOp))
   })
 
+  require(exuParameters.AluCnt <= dpParams.IntDqDeqWidth)
+
   io.enqIQCtrl <> DontCare
-  for (i <- 0 until 4) {
+  for (i <- 0 until exuParameters.AluCnt) {
     io.enqIQCtrl(i) <> io.fromDq(i)
-  }
-  io.enqIQCtrl(4).valid := false.B
-  io.enqIQCtrl(5).valid := false.B
-  io.enqIQCtrl(6).valid := false.B
-  io.readRf(0) := io.enqIQCtrl(0).bits.psrc(0)
-  io.readRf(1) := io.enqIQCtrl(0).bits.psrc(1)
-  io.readRf(2) := io.enqIQCtrl(1).bits.psrc(0)
-  io.readRf(3) := io.enqIQCtrl(1).bits.psrc(1)
-  io.readRf(4) := io.enqIQCtrl(2).bits.psrc(0)
-  io.readRf(5) := io.enqIQCtrl(2).bits.psrc(1)
-  io.readRf(6) := io.enqIQCtrl(3).bits.psrc(0)
-  io.readRf(7) := io.enqIQCtrl(3).bits.psrc(1)
-
-  // val jmpCnt = exuParameters.JmpCnt
-  // val mduCnt = exuParameters.MduCnt
-  // val aluCnt = exuParameters.AluCnt
-
-  /**
-    * Part 1: generate indexes for reservation stations
-    */
-//   assert(jmpCnt == 1)
-//   val jmpCanAccept = VecInit(io.fromDq.map(deq => deq.valid && FuType.jmpCanAccept(deq.bits.ctrl.fuType)))
-//   val mduCanAccept = VecInit(io.fromDq.map(deq => deq.valid && FuType.mduCanAccept(deq.bits.ctrl.fuType)))
-//   val aluCanAccept = VecInit(io.fromDq.map(deq => deq.valid && FuType.aluCanAccept(deq.bits.ctrl.fuType)))
-
-//   val jmpIndexGen = Module(new IndexMapping(dpParams.IntDqDeqWidth, jmpCnt, false))
-//   val mduIndexGen = Module(new IndexMapping(dpParams.IntDqDeqWidth, mduCnt, true))
-//   // val aluIndexGen = Module(new IndexMapping(dpParams.IntDqDeqWidth, aluCnt, true))
-
-//   val (mduPriority, mduIndex) = PriorityGen(io.numExist.slice(jmpCnt, jmpCnt + mduCnt))
-//   val (aluPriority, aluIndex) = PriorityGen(io.numExist.drop(jmpCnt + mduCnt))
-//   jmpIndexGen.io.validBits := jmpCanAccept
-//   mduIndexGen.io.validBits := mduCanAccept
-//   // aluIndexGen.io.validBits := aluCanAccept
-//   jmpIndexGen.io.priority := DontCare
-//   mduIndexGen.io.priority := mduPriority
-//   // aluIndexGen.io.priority := aluPriority
-
-//   // val allIndexGen = Seq(jmpIndexGen, mduIndexGen, aluIndexGen)
-//   // val validVec = allIndexGen.flatMap(_.io.mapping.map(_.valid))
-//   // val indexVec = allIndexGen.flatMap(_.io.mapping.map(_.bits))
-
-//   /**
-//     * Part 2: assign regfile read ports
-//     */
-//   // val intStaticIndex = Seq(3, 4, 5, 6)
-//   // val intDynamicIndex = Seq(0, 1, 2)
-//   // val intStaticMappedValid = intStaticIndex.map(i => validVec(i))
-//   // val intDynamicMappedValid = intDynamicIndex.map(i => validVec(i))
-//   // val (intReadPortSrc, intDynamicExuSrc) = RegfileReadPortGen(intStaticMappedValid, intDynamicMappedValid)
-//   // val intStaticMapped = intStaticIndex.map(i => indexVec(i))
-//   // val intDynamicMapped = intDynamicIndex.map(i => indexVec(i))
-//   // for (i <- intStaticIndex.indices) {
-//   //   val index = WireInit(VecInit(intStaticMapped(i) +: intDynamicMapped))
-//   //   io.readRf(2*i  ) := io.fromDq(index(intReadPortSrc(i))).bits.psrc(0)
-//   //   io.readRf(2*i+1) := io.fromDq(index(intReadPortSrc(i))).bits.psrc(1)
-//   // }
-//   // val readPortIndex = Wire(Vec(exuParameters.IntExuCnt, UInt(2.W)))
-//   // intStaticIndex.zipWithIndex.map({case (index, i) => readPortIndex(index) := i.U})
-//   // intDynamicIndex.zipWithIndex.map({case (index, i) => readPortIndex(index) := intDynamicExuSrc(i)})
-//   io.readRf(0) := io.enqIQCtrl(3).bits.psrc(0)
-//   io.readRf(1) := io.enqIQCtrl(3).bits.psrc(1)
-//   io.readRf(2) := Mux(io.enqIQCtrl(4).valid, io.enqIQCtrl(4).bits.psrc(0), io.enqIQCtrl(0).bits.psrc(0))
-//   io.readRf(3) := io.enqIQCtrl(4).bits.psrc(1)
-//   io.readRf(4) := Mux(io.enqIQCtrl(5).valid, io.enqIQCtrl(5).bits.psrc(0), io.enqIQCtrl(1).bits.psrc(0))
-//   io.readRf(5) := Mux(io.enqIQCtrl(5).valid, io.enqIQCtrl(5).bits.psrc(1), io.enqIQCtrl(1).bits.psrc(1))
-//   io.readRf(6) := Mux(io.enqIQCtrl(6).valid, io.enqIQCtrl(6).bits.psrc(0), io.enqIQCtrl(2).bits.psrc(0))
-//   io.readRf(7) := Mux(io.enqIQCtrl(6).valid, io.enqIQCtrl(6).bits.psrc(1), io.enqIQCtrl(2).bits.psrc(1))
+    io.readRf(2*i) := io.enqIQCtrl(i).bits.psrc(0)
+    io.readRf(2*i + 1) := io.enqIQCtrl(i).bits.psrc(1)
 
-  for (i <- 0 until dpParams.IntDqDeqWidth) {
     io.readState(2*i  ).req := io.fromDq(i).bits.psrc(0)
     io.readState(2*i+1).req := io.fromDq(i).bits.psrc(1)
-  }
-  for (i <- 0 until 4) {
+
     io.enqIQCtrl(i).bits.srcState(0) := io.readState(i * 2).resp
     io.enqIQCtrl(i).bits.srcState(1) := io.readState(i * 2 + 1).resp
   }
 
-//   /**
-//     * Part 3: dispatch to reservation stations
-//     */
-//   val jmpReady = io.enqIQCtrl(0).ready
-//   val mduReady = Cat(io.enqIQCtrl.slice(jmpCnt, jmpCnt + mduCnt).map(_.ready)).andR
-//   // val aluReady = Cat(io.enqIQCtrl.drop(jmpCnt + mduCnt).map(_.ready)).andR
-//   for (i <- 0 until exuParameters.IntExuCnt) {
-//     val enq = io.enqIQCtrl(i)
-//     val deqIndex = if (i < jmpCnt) jmpIndexGen.io.mapping(0).bits else if (i < jmpCnt + mduCnt) mduIndexGen.io.mapping(i - jmpCnt).bits else aluPriority(i - (jmpCnt + mduCnt))
-//     if (i < jmpCnt) {
-//       enq.valid := jmpIndexGen.io.mapping(i).valid && !io.enqIQCtrl(4).valid
-//     }
-//     else if (i < jmpCnt + mduCnt) {
-//       enq.valid := mduIndexGen.io.mapping(i - jmpCnt).valid && mduReady && !io.enqIQCtrl(5).valid && !io.enqIQCtrl(6).valid
-//     }
-//     else { // alu
-//       enq.valid := aluCanAccept(aluPriority(i - (jmpCnt + mduCnt))) //aluIndexGen.io.mapping(i - (jmpCnt + mduCnt)).valid //&& aluReady
-//     }
-//     enq.bits := io.fromDq(deqIndex).bits
-
-//     enq.bits.srcState(0) := src1Ready(deqIndex)
-//     enq.bits.srcState(1) := src2Ready(deqIndex)
-//     enq.bits.srcState(2) := DontCare
-
-//     XSInfo(enq.fire(), p"pc 0x${Hexadecimal(enq.bits.cf.pc)} with type ${enq.bits.ctrl.fuType} " +
-//       p"srcState(${enq.bits.srcState(0)} ${enq.bits.srcState(1)}) " +
-//       p"enters reservation station $i from ${deqIndex}\n")
-//   }
-
-//   /**
-//     * Part 4: response to dispatch queue
-//     */
-//   val mdu2CanOut = !(mduCanAccept(0) && mduCanAccept(1))
-//   val mdu3CanOut = !(mduCanAccept(0) && mduCanAccept(1) || mduCanAccept(0) && mduCanAccept(2) || mduCanAccept(1) && mduCanAccept(2))
-//   val aluReadyVec = VecInit(io.enqIQCtrl.drop(jmpCnt + mduCnt).map(_.ready))
-//   for (i <- 0 until dpParams.IntDqDeqWidth) {
-//     io.fromDq(i).ready := jmpCanAccept(i) && (if (i == 0) true.B else !Cat(jmpCanAccept.take(i)).orR) && jmpReady && !io.enqIQCtrl(4).valid ||
-//                           aluCanAccept(i) && aluReadyVec(aluIndex(i)) ||
-//                           mduCanAccept(i) && (if (i <= 1) true.B else if (i == 2) mdu2CanOut else mdu3CanOut) && mduReady && !io.enqIQCtrl(5).valid && !io.enqIQCtrl(6).valid
-
-//     XSInfo(io.fromDq(i).fire(),
-//       p"pc 0x${Hexadecimal(io.fromDq(i).bits.cf.pc)} leaves Int dispatch queue $i with nroq ${io.fromDq(i).bits.roqIdx}\n")
-//     XSDebug(io.fromDq(i).valid && !io.fromDq(i).ready,
-//       p"pc 0x${Hexadecimal(io.fromDq(i).bits.cf.pc)} waits at Int dispatch queue with index $i\n")
-//   }
-  XSError(PopCount(io.fromDq.map(_.fire())) =/= PopCount(io.enqIQCtrl.map(_.fire())), "deq =/= enq\n")
-
-//   /**
-//     * Part 5: send read port index of register file to reservation station
-//     */
-//   // io.readPortIndex := readPortIndex
-  io.readPortIndex := DontCare
-// //  val readPortIndexReg = Reg(Vec(exuParameters.IntExuCnt, UInt(log2Ceil(NRIntReadPorts).W)))
-// //  val uopReg = Reg(Vec(exuParameters.IntExuCnt, new MicroOp))
-// //  val dataValidRegDebug = Reg(Vec(exuParameters.IntExuCnt, Bool()))
-// //  for (i <- 0 until exuParameters.IntExuCnt) {
-// //    readPortIndexReg(i) := readPortIndex(i)
-// //    uopReg(i) := io.enqIQCtrl(i).bits
-// //    dataValidRegDebug(i) := io.enqIQCtrl(i).fire()
-// //
-// //    io.enqIQData(i) := DontCare
-// //    io.enqIQData(i).src(0) := Mux(uopReg(i).ctrl.srcType(0) === SrcType.pc,
-// //      SignExt(uopReg(i).cf.pc, XLEN), io.readRf(readPortIndexReg(i)).data)
-// //    io.enqIQData(i).src(1) := Mux(uopReg(i).ctrl.srcType(1) === SrcType.imm,
-// //      uopReg(i).ctrl.imm, io.readRf(readPortIndexReg(i) + 1.U).data)
-// //
-// //    XSDebug(dataValidRegDebug(i),
-// //      p"pc 0x${Hexadecimal(uopReg(i).cf.pc)} reads operands from " +
-// //        p"(${readPortIndexReg(i)    }, ${uopReg(i).psrc(0)}, ${Hexadecimal(io.enqIQData(i).src(0))}), " +
-// //        p"(${readPortIndexReg(i)+1.U}, ${uopReg(i).psrc(1)}, ${Hexadecimal(io.enqIQData(i).src(1))})\n")
-// //  }
+  for (i <- exuParameters.AluCnt until dpParams.IntDqDeqWidth) {
+    io.fromDq(i).ready := false.B
+  }
 
-//   XSPerfAccumulate("in", PopCount(io.fromDq.map(_.valid)))
-//   XSPerfAccumulate("out", PopCount(io.enqIQCtrl.map(_.fire())))
-//   XSPerfAccumulate("out_jmp", io.enqIQCtrl(0).fire())
-//   XSPerfAccumulate("out_mdu0", io.enqIQCtrl(1).fire())
-//   XSPerfAccumulate("out_mdu1", io.enqIQCtrl(2).fire())
-//   XSPerfAccumulate("out_alu0", io.enqIQCtrl(3).fire())
-//   XSPerfAccumulate("out_alu1", io.enqIQCtrl(4).fire())
-//   XSPerfAccumulate("out_alu2", io.enqIQCtrl(5).fire())
-//   XSPerfAccumulate("out_alu3", io.enqIQCtrl(6).fire())
-//   val block_num = PopCount(io.fromDq.map(deq => deq.valid && !deq.ready))
-//   XSPerfAccumulate("blocked", block_num)
-//   XSPerfAccumulate("blocked_index", Mux(block_num =/= 0.U, PriorityEncoder(io.fromDq.map(deq => deq.valid && !deq.ready)), 0.U))
-//   XSPerfAccumulate("jump_deq_try", PopCount(jmpCanAccept))
-//   XSPerfAccumulate("jump_deq_exceed_limit", Mux(PopCount(jmpCanAccept) >= 1.U, PopCount(jmpCanAccept) - 1.U, 0.U))
-//   XSPerfAccumulate("mdu_deq_try", PopCount(mduCanAccept))
-//   XSPerfAccumulate("mdu_deq_exceed_limit", Mux(PopCount(mduCanAccept) >= 2.U, PopCount(mduCanAccept) - 2.U, 0.U))
-//   XSPerfAccumulate("alu0_blocked_by_alu0", io.enqIQCtrl(3).valid && !io.enqIQCtrl(3).ready)
-//   XSPerfAccumulate("alu1_blocked_by_alu1", io.enqIQCtrl(4).valid && !io.enqIQCtrl(4).ready)
-//   XSPerfAccumulate("alu2_blocked_by_alu2", io.enqIQCtrl(5).valid && !io.enqIQCtrl(5).ready)
-//   XSPerfAccumulate("alu3_blocked_by_alu3", io.enqIQCtrl(6).valid && !io.enqIQCtrl(6).ready)
-//   XSPerfAccumulate("jump_blocked_by_alu1", jmpIndexGen.io.mapping(0).valid && io.enqIQCtrl(4).valid && io.enqIQCtrl(0).ready)
-//   XSPerfAccumulate("mdu0_blocked_by_alu", mduIndexGen.io.mapping(0).valid && mduReady && (io.enqIQCtrl(5).valid || io.enqIQCtrl(6).valid))
-//   XSPerfAccumulate("mdu0_blocked_by_alu2", mduIndexGen.io.mapping(0).valid && mduReady && io.enqIQCtrl(5).valid && !io.enqIQCtrl(6).valid)
-//   XSPerfAccumulate("mdu0_blocked_by_alu3", mduIndexGen.io.mapping(0).valid && mduReady && !io.enqIQCtrl(5).valid && io.enqIQCtrl(6).valid)
-//   XSPerfAccumulate("mdu0_blocked_by_mdu1", mduIndexGen.io.mapping(0).valid && io.enqIQCtrl(1).ready && !io.enqIQCtrl(2).ready && !io.enqIQCtrl(5).valid && !io.enqIQCtrl(6).valid)
-//   XSPerfAccumulate("mdu1_blocked_by_alu", mduIndexGen.io.mapping(1).valid && mduReady && (io.enqIQCtrl(5).valid || io.enqIQCtrl(6).valid))
-//   XSPerfAccumulate("mdu1_blocked_by_alu2", mduIndexGen.io.mapping(1).valid && mduReady && io.enqIQCtrl(5).valid && !io.enqIQCtrl(6).valid)
-//   XSPerfAccumulate("mdu1_blocked_by_alu3", mduIndexGen.io.mapping(1).valid && mduReady && !io.enqIQCtrl(5).valid && io.enqIQCtrl(6).valid)
-//   XSPerfAccumulate("mdu1_blocked_by_mdu0", mduIndexGen.io.mapping(1).valid && !io.enqIQCtrl(1).ready && io.enqIQCtrl(2).ready && !io.enqIQCtrl(5).valid && !io.enqIQCtrl(6).valid)
 }

src/main/scala/xiangshan/backend/exu/Exu.scala

@@ -42,6 +42,8 @@ case class ExuParameters
   def LsExuCnt = LduCnt + StuCnt
 
   def ExuCnt = IntExuCnt + FpExuCnt + LduCnt + StuCnt
+
+  def CriticalExuCnt = AluCnt + FmacCnt + LsExuCnt
 }
 
 case class ExuConfig

src/main/scala/xiangshan/backend/issue/DataArray.scala

@@ -53,7 +53,7 @@ class DataArrayMultiWriteIO(numEntries: Int, numSrc: Int, dataBits: Int)(implici
 class DataArrayIO(params: RSParams)(implicit p: Parameters) extends XSBundle {
   val read = Vec(params.numDeq, new DataArrayReadIO(params.numEntries, params.numSrc, params.dataBits))
   val write = Vec(params.numEnq, new DataArrayWriteIO(params.numEntries, params.numSrc, params.dataBits))
-  val multiWrite = Vec(params.numDataCapture, new DataArrayMultiWriteIO(params.numEntries, params.numSrc, params.dataBits))
+  val multiWrite = Vec(params.numWakeup, new DataArrayMultiWriteIO(params.numEntries, params.numSrc, params.dataBits))
   val delayedWrite = if (params.delayedRf) Vec(params.numEnq, Flipped(ValidIO(UInt(params.dataBits.W)))) else null
 
   override def cloneType: DataArrayIO.this.type =
@@ -112,16 +112,17 @@ class AluImmExtractor(implicit p: Parameters) extends ImmExtractor(2, 64) {
 }
 
 object ImmExtractor {
-  def apply(config: RSParams, exuCfg: ExuConfig, uop: MicroOp, data_in: Vec[UInt], pc: UInt, target: UInt)(implicit p: Parameters): Vec[UInt] = {
-    val immExt = exuCfg match {
-      case JumpExeUnitCfg => {
+  def apply(params: RSParams, uop: MicroOp, data_in: Vec[UInt], pc: Option[UInt], target: Option[UInt])
+           (implicit p: Parameters): Vec[UInt] = {
+    val immExt = (params.isJump, params.isAlu) match {
+      case (true, false) => {
         val ext = Module(new JumpImmExtractor)
-        ext.jump_pc := pc
-        ext.jalr_target := target
+        ext.jump_pc := pc.get
+        ext.jalr_target := target.get
         ext
       }
-      case AluExeUnitCfg => Module(new AluImmExtractor)
-      case _ => Module(new ImmExtractor(config.numSrc, config.dataBits))
+      case (false, true) => Module(new AluImmExtractor)
+      case _ => Module(new ImmExtractor(params.numSrc, params.dataBits))
     }
     immExt.io.uop := uop
     immExt.io.data_in := data_in

src/main/scala/xiangshan/backend/issue/StatusArray.scala

@@ -67,8 +67,8 @@ class StatusArray(params: RSParams)(implicit p: Parameters) extends XSModule
     val canIssue = Output(UInt(params.numEntries.W))
     // enqueue, dequeue, wakeup, flush
     val update = Vec(params.numEnq, new StatusArrayUpdateIO(params))
-    val wakeup = Vec(params.numWakeup, Flipped(ValidIO(new MicroOp)))
-    val wakeupMatch = Vec(params.numEntries, Vec(params.numSrc, Output(UInt(params.numWakeup.W))))
+    val wakeup = Vec(params.allWakeup, Flipped(ValidIO(new MicroOp)))
+    val wakeupMatch = Vec(params.numEntries, Vec(params.numSrc, Output(UInt(params.allWakeup.W))))
     val issueGranted = Vec(params.numDeq, Flipped(ValidIO(UInt(params.numEntries.W))))
     val deqResp = Vec(params.numDeq, Flipped(ValidIO(new Bundle {
       val rsMask = UInt(params.numEntries.W)