* inserted br should only add 1 new valid bit to brValids

* this target represents the target of the first jal instruction
  in the range of (FetchWidth * 4Bytes) regardless of whether it
  is in the real fetch stream

* save pftAddr for ifu req
* save nextRangeAddr(startAddr+FetchBytes) for pc read

This reverts commit 0a2b8431.

* FTB: fix getJmpOffset function
* Ftq: fix set_replay_status_between function
* IFU: toFtq.valid only holds 1 cycle

* pass the range vector into predecode to mask invalid instructions
* set the oversize bits when the new ftb entry has an RVI cfi at the end
* pass oversize bit to ifu to indicate this block has more than FetchWidth*4 Bytes

* validate instructions only between startAddr and fallThroughAddr.
* mask instructions before replayed load.
* mask instructions behind jump.

* only instruction that is predicted taken and is a real cfi, will set
taken in PreDecode

1. taken mask should consider corresponding valid bit
2. FetchWidth is in 4 bytes

1. previously we flush ftq status at stage2Redirect, but use
   stage3Redirect to flush ifu, when stage3Redirect comes with
   pdWb, ifuWbPtr would be falsely increased
2. toBpuUpdate.valid should only assign when do_commit