[WIP] ftq: add update logic

src/main/scala/xiangshan/decoupled-frontend/FTB.scala

@@ -66,6 +66,9 @@ class FTBEntry (implicit p: Parameters) extends XSBundle with FTBParams {
 
   //   (taken_mask, target)
   // }
+
+  def getJmpOffset(pc: UInt) = Cat(1.U(1.W), pftAddr(4,1)) - Mux(last_is_rvc, 2.U, 4.U) - pc(4,1)
+  def isJal = !isJalr
 }
 
 class FTBMeta(implicit p: Parameters) extends XSBundle with FTBParams {

src/main/scala/xiangshan/decoupled-frontend/FrontendBundle.scala

@@ -10,6 +10,7 @@ class FetchRequestBundle(implicit p: Parameters) extends XSBundle {
   val startAddr    = UInt(VAddrBits.W)
   val fallThruAddr = UInt(VAddrBits.W)
   val ftqIdx       = new FtqPtr
+  val ldReplayOffset = ValidUndirectioned(UInt(log2Ceil(32).W))
   val ftqOffset    = ValidUndirectioned(UInt(log2Ceil(32).W))
   val target       = UInt(VAddrBits.W)
 
@@ -121,6 +122,8 @@ class BranchPredictionResp(implicit p: Parameters) extends XSBundle with HasBPUC
 
 class BranchPredictionUpdate(implicit p: Parameters) extends BranchPredictionBundle with HasBPUConst {
   val mispred_mask = Vec(numBr+1, Bool())
+  val false_hit = Bool()
+  val new_br_insert_pos = Vec(numBr, Bool())
   // val ghist = new GlobalHistory() This in spec_meta
 }