ftq: send request derived from predicted info to ifu

src/main/scala/xiangshan/decoupled-frontend/NewFtq.scala

@@ -96,6 +96,11 @@ class Ftq_1R_SRAMEntry(implicit p: Parameters) extends XSBundle {
   val meta = UInt(120.W)
 }
 
+class Ftq_Pred_Info(implicit p: Parameters) extends XSBundle {
+  val target = UInt(VAddrBits.W)
+  val cfiIndex = ValidUndirectioned(UInt(log2Ceil(PredictWidth).W))
+}
+
 class FtqEntry(implicit p: Parameters) extends XSBundle {
   val startAddr = UInt(VAddrBits.W)
   val fallThruAddr = UInt(VAddrBits.W)
@@ -338,10 +343,11 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
   ftq_redirect_sram.io.wdata.rasEntry := io.fromBpu.resp.bits.rasTop
   ftq_redirect_sram.io.wdata.specCnt := io.fromBpu.resp.bits.specCnt
 
-  val pred_target_sram = Module(new FtqNRSRAM(UInt(VAddrBits.W), 1))
-  pred_target_sram.io.wen := enq_fire
-  pred_target_sram.io.waddr := bpuPtr.value
-  pred_target_sram.io.wdata := io.fromBpu.resp.bits.preds.target
+  val pred_info_sram = Module(new FtqNRSRAM(new Ftq_Pred_Info, 1))
+  pred_info_sram.io.wen := enq_fire
+  pred_info_sram.io.waddr := bpuPtr.value
+  pred_info_sram.io.wdata.target := io.fromBpu.resp.bits.preds.target
+
 
   val ftq_meta_1r_sram = Module(new FtqNRSRAM(new Ftq_1R_SRAMEntry, 1))
   ftq_meta_1r_sram.io.wen := enq_fire
@@ -405,6 +411,7 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
     enq_cfiIndex.valid := real_taken_mask.orR
     enq_cfiIndex.bits := ParallelPriorityMux(real_taken_mask, offset_vec)
     cfiIndex_vec(enqIdx) := enq_cfiIndex
+    pred_info_sram.io.wdata.cfiIndex := enq_cfiIndex
     mispredict_vec(enqIdx) := WireInit(VecInit(Seq.fill(16)(false.B)))
     update_target(enqIdx) := preds.target
   }
@@ -471,8 +478,6 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
     }
   }
 
-  XSError(pdWb.valid && pdWb.bits.misOffset.valid && entry_replay_status(ifu_wb_idx) === l_replaying,
-    "unexpected misprediction detected by predecode during replay\n")
 
   // ****************************************************************
   // **************************** to ifu ****************************
@@ -496,13 +501,12 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
   
   // read pc and target
   ftq_pc_mem.io.raddr.init.last := ifuPtr.value
-  pred_target_sram.io.raddr(0) := ifuPtr.value
-  pred_target_sram.io.ren(0) := to_buf_fire
+  pred_info_sram.io.raddr(0) := ifuPtr.value
+  pred_info_sram.io.ren(0) := to_buf_fire
   
   val loadReplayOffset = RegInit(0.U.asTypeOf(Valid(UInt(log2Ceil(FtqSize).W))))
   when (to_buf_fire) {
     ifu_req_buf.bits.ftqIdx := ifuPtr
-    ifu_req_buf.bits.ftqOffset := cfiIndex_vec(ifuPtr.value)
     ifu_req_buf.bits.ldReplayOffset := loadReplayOffset
     when (loadReplayOffset.valid) {
       loadReplayOffset.valid := false.B
@@ -512,7 +516,8 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
     ifu_req_buf.bits.startAddr    := ftq_pc_mem.io.rdata.init.last.startAddr
     ifu_req_buf.bits.fallThruAddr := ftq_pc_mem.io.rdata.init.last.fallThruAddr
     ifu_req_buf.bits.oversize     := ftq_pc_mem.io.rdata.init.last.oversize
-    ifu_req_buf.bits.target := pred_target_sram.io.rdata(0)
+    ifu_req_buf.bits.target    := pred_info_sram.io.rdata(0).target
+    ifu_req_buf.bits.ftqOffset := pred_info_sram.io.rdata(0).cfiIndex
   }
   
   val last_cycle_to_buf_fire = RegNext(to_buf_fire)
@@ -522,7 +527,8 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
     io.toIfu.req.bits.startAddr    := ftq_pc_mem.io.rdata.init.last.startAddr
     io.toIfu.req.bits.fallThruAddr := ftq_pc_mem.io.rdata.init.last.fallThruAddr
     io.toIfu.req.bits.oversize     := ftq_pc_mem.io.rdata.init.last.oversize
-    io.toIfu.req.bits.target := pred_target_sram.io.rdata(0)
+    io.toIfu.req.bits.target    := pred_info_sram.io.rdata(0).target
+    io.toIfu.req.bits.ftqOffset := pred_info_sram.io.rdata(0).cfiIndex
   }