ubtb: fix write waymask of fallThruPred

ittage: we should write new target when alloc

last_may_be_rvi_call in case that a call comes after a taken branch

* bump difftest

* ci: support basic simv emulation

* ci: use exact ip address to ssh

* ci: modify simv emulation timeout threshold

* bump huancun, update Chisel3, revert sram hazard enhancement

* util.sram: rm a r/w hazard mux which is not needed. bump huancun

Previous logic checked the value of old_ctr to select between old target and
new target when updating ittage table. However, when we need to alloc a new
entry, the value of old_ctr is X because we do not reset ittage table. So we
would definitely write an X to the target field, which is the output of the
mux, as the selector is X.

* fix for chipsalliance/rocket-chip#2967

* decode: fix width of BitPat(?) in decode logic
Co-authored-by: NYinan Xu <xuyinan@ict.ac.cn>

Previously we made a mistake to connect rtc_clock to rtcTick for CLINT.

rtcTick should be on io_clock clock domain and asserted only one
clock cycle in io_clock for every cycle in rtc_clock. We add sampling
registers in this commit to fix this.

sramtemplate: fix waymask in FoldedSRAMTemplate

Provide two issue template.

* difftest: disable runahead to make vcs happy

* difftest: bump huancun to make vcs happy

* difftest: bump difftest and ready-to-run

* difftest support ramsize and paddr base config
* 8GB/16GB nemu so are provided by ready-to-run

* ci: update nightly ci, manually set ram_size

* difftest: bump huancun to make vcs happy

* difftest,nemu: support run-time assign mem size

* ci: polish nightly ci script

An instruction with exceptions may have arbitrary instr values and
may be decoded into WFI instructions, which cause errors.

Use 16GB memory as default. SPEC CPU2017 requires more than 8GB memory.

* sc: fix a performance bug

* tage: fix number of use-alt-on-na counters

* tage: update provider u-bit according to provider results

* feat: parameterize load/store pipeline, etc.

* fix: use LoadPipelineWidth rather than LoadQueueSize

* fix: parameterize `rdataPtrExtNext`

* SBuffer: fix idx update logic

* atomic: parameterize atomic logic in `MemBlock`

* StoreQueue: update allow enque requirement

* feat: support one load/store pipeline

* feat: parameterize `EnsbufferWidth`

* chore: resharp codes for better generated name

* chore: remove sc too many fail assertion

* chore: use XSWarn()

difftest: fix support for Spike

s1_tag_match_way is vaild iff tag_read.valid and meta_read.valid in s0
for the same req

XiangShan does not support fs=0 because when fs=0, all floating-point
states are not accessible. Spike supports fs=0. To diff with Spike,
we temporarily set fs to 1 when initialized.

Add support for the WFI instruction

This commit fixes the implementation of WFI. The WFI instruction
waits in the ROB until an interrupt might need servicing.

According to the RISC-V manual, the WFI must be unaffected by the
global interrupt bits in `mstatus` and the delegation register
`mideleg`.

To test WFI, we delay the interrupts for more cycles.

The RISC-V WFI instruction is previously decoded as NOP. This commit
adds support for the real wait-for-interrupt (WFI).

We add a state_wfi FSM in the ROB. After WFI leaves the ROB, the next
instruction will wait in the ROB until an interrupt.

*** Description ***
- During multi-thread verilator emulation, the
reset_ncycle(size_t cycles) function will trigger the flash_read()
function where a NULL pointer *flash_base will be used since we init
flash after the reset_ncycle.

- This bug is triggered in some seeds, while others runs in a normal
way.

*** Solution ***
- init flash before reset_cycles()