* add perf counters for btb and ubtb
* update btb only on not hit or jalr mispredicts to reduce write stalls

just record the tlb result(access and miss) of first issue by add
signal isFirstIssue (isFirstIssue = cntCountQueue(i) === 0.U)

* DCacheWrapper: MainPipe use read port 1 to ease congestion

* MainPipe: do not consider congestion with ldu0 read when disabling fast wakeup

Previously we use numactl to specify both nodes and cpus for emu.
However, when other processes are using the same cpu, verilated emu
suffers from huge performance degradation. To avoid these scenarios,
we only specify the numa node to achieve a more stable performance.

In this commit, we add support for a simpler version of move elimination.

The original instruction sequences are:
move r1, r0
add r2, r1, r3

The optimized sequnces are:
move pr1, pr0
add pr2, pr0, pr3 # instead of add pr2, pr1, pr3

In this way, add can be issued once r0 is ready and move seems to be eliminated.

* MainPipe/LoadPipe: disable fast wakeup when data sram is to be written

* RS: set EnableLoadFastWakeUp true

* LoadPipe: add perf cnt for disabling ld fast wakeup speculatively

* MainPipe: disable ld fast wakeup when s1 read data in MainPipe
Co-authored-by: Nzhanglinjuan <zhanglinjuan16@mails.ucas.ac.cn>

* DCache: fix bug in failing to update access info of plru replacement

* DCache: add performance counters

* Top: remove extra axi ID bits

* Re-add AXI4UserYanker
Co-authored-by: NLinJiawei <linjiav@outlook.com>

previously the biggest problem was using '+' instead of '+&' to
do sums

* LoadUnit: generate fastUop in load_s1

* RS/Load: add load to fast wakeup when cache hit, while maintain its slow

* RS: remove legacy assert that doesn't work for load has fast and slow

* LoadUnit: fix bug that fastUops's valid forgets load_s1.io.in.valid

* MemBlock: fix bug of loadUnit's fast and slow connect

IPC of coremark 10 cycles raise from 1.63 to 1.70

* RS: RegNext srcUpdate to use it at next cycle

* RS: add param EnableLoadFastWakeUp and set default to false
Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>

* L1I/L1+:  Add performance counters for each way.

* Replacement: fix that lfsr always changes in random.

* TLB&PTW: add replace perf count

* PTW: remove set's perf count, just way's

* PTW: fix bug that puts perf inside when

* TLB&PTW: add access perf count

DCache: rearrange dcache array and set write priority higher than read

* RS: add many rs's perf cnter

* RS: add param myName for submodule name

* RS: set Integer&Mem block's rs' srcLen to XLEN

* MySoc: verilog top

* MySoc: connect mmio

* MySoc: fix some bugs

* wip

* TopMain: remove to top

* WIP: add dma port

* Update XSTop for FPGA/ASIC platform

* Top: add rocket-chip source

* Append SRAM to generated verilog
Co-authored-by: NLinJiawei <linjiav@outlook.com>