merge rf-after-issue, also sync with master

refactor(UopDivType): rename UopDivType & change VECTOR_TMP_REG_MV to FP_TMP_REG_MV

1. rename UopDivType
2. change VECTOR_TMP_REG_MV to FP_TMP_REG_MV
3. add UopDivType.VEC_MMM for decode of VMAND_MM VMANDN_MM ... VMXOR_MM

Add a custom arbiter. In the case of multiple sources with the same
cache block address, the arbiter will assign only one entry in
misssqueue but ready for all same cache block address requests.

This will reduce the number of replays of the load instruction which cannot
enter the missqueue

func(vfmin vfmax): pass vfmin & vfmax in VectorFloatAdder

func(vstart): add vstart from CSR to VIPU
func(VipuType): add VipuType of vwsubu.vv vwsubu.wv vwsub.vx vwsub.wx
pom(yunsuan): support vfmin vfmax
func(vfmin vfmax): pass vfmin & vfmax in VectorFloatAdder

1. fix vset related bugs
2. modifiy the update logic of vxsat
3. modify numFpRfPorts parameter in the ReservationStationBase

* MMU: Add sector tlb for larger capacity

* MMU: Update difftest for sector tlb

This commit aims to fix dcache plru access logic

In the previous version, when a cacheline not in l1 is accessed, a replace way
is picked and used to update l1 plru (set the way as lru). However, if the same
missed cacheline is accessed multiple times before l1 refill, l1 will pick a new
replace way and use it to update plru for each time the missed cacheline is
accessed. It makes the plru totally a mess.

To fix that problem, extra condition check is added for a missed load plru
update. Now plru is updated on:

* load/store hit (touch hit way)
* load/store primary miss (touch replacement way)
* load/store secondary miss (touch replacement way)

`updateReplaceOn2ndmiss` is enabled. Disable it if the timing is bad.

func(decode):add VIAlu decode of VecDecoder & VIPU
pom(yunsuan): add more VipuType & fix bug of lmul=8 vl=128
pom(difftest): remove uopIdx which no longer used

1. fix bug that connection of fuOpType in VIPU
2. vadd vmin vminu vmax vmaxu vand vor vxor vsub vrsub test pass

1. add end flag for uopIdx
2. fix(VFPU): io.in.ready should be ture.B
3. func(VIAlu):add VIAlu code v2
4. add vxsat form VIPU to CSR

1. add end flag for uopIdx
2. fix(VFPU): io.in.ready should be ture.B
3. func(VIAlu):add VIAlu code v2

fix write conflit bug between VFPU and VIPU & add vmask to the pipeline