- 20 6月, 2022 1 次提交
-
-
由 Yinan Xu 提交于
-
- 16 12月, 2021 1 次提交
-
-
由 Li Qianruo 提交于
We have singlestep already so triggers do not need to hit after inst commits
-
- 10 12月, 2021 1 次提交
-
-
由 Yinan Xu 提交于
This commit optimizes the coding style and timing for hardware performance counters. By default, performance counters are RegNext(RegNext(_)).
-
- 23 11月, 2021 1 次提交
-
-
由 William Wang 提交于
* mdp: implement SSIT with sram * mdp: use robIdx instead of sqIdx Dispatch refactor moves lsq enq to dispatch2, as a result, mdp can not get correct sqIdx in dispatch. Unlike robIdx, it is hard to maintain a "speculatively assigned" sqIdx, as it is hard to track store insts in dispatch queue. Yet we can still use "speculatively assigned" robIdx for memory dependency predictor. For now, memory dependency predictor uses "speculatively assigned" robIdx to track inflight store. However, sqIdx is still used to track those store which's addr is valid but data it not valid. When load insts try to get forward data from those store, load insts will get that store's sqIdx and wait in RS. They will not waken until store data with that sqIdx is issued. * mdp: add track robIdx recover logic
-
- 27 10月, 2021 1 次提交
-
-
由 happy-lx 提交于
* Svinval: implement Svinval * add three new instructions(SINVAL_VMA SFENCE_W_INVAL SFENCE_INVAL_IR) * TODO : test * Prevent illegal software code by adding an assert * make sure the software runs as follow: begin instruction of svinval extension svinval xxxx svinval xxxx ... end instruction of svinval extension * Svinval: add an CSR to control it and some annotations * Roq: fix assert bug of Svinval * Svinval: fix svinval.vma's rs2 type * make it reg instead of imm * Svinval: change assert logic and fix bug * fix the condition judging Svinval.vma instruction * using doingSvinval in assert * ci: add rv64mi-p-svinval to ci * fix typo * fix bug that lost ',' * when svinval disable, raise illegal instr excep * CSR: mv svinval ctl to srnctl(1) * rob: when excep, do not set dosvinval * decode: when disable svinval, do not set flushpipe * bump ready-to-run Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn>
-
- 23 10月, 2021 1 次提交
-
-
由 rvcoresjw 提交于
* Add perf counters * add reg from hpm counter source * add print perfcounter enable
-
- 22 10月, 2021 1 次提交
-
-
由 Yinan Xu 提交于
This PR optimizes out isFused and crossPageIPFFix usages in Rob's DispatchData. They will not be stored in ROB. Now DispatchData has only 38 bits. * isFused is merged with commitType (2 bits reduced) * crossPageIPFFix is used only in ExceptionGen (1 bit reduced) * rename: reduce ldest usages * decode: set isMove to false if ldest is zero
-
- 16 10月, 2021 1 次提交
-
-
由 William Wang 提交于
* storeset: fix waitForSqIdx generate logic Now right waitForSqIdx will be generated for earlier store in the same dispatch bundle. * mdp: add strict wait mode When loadWaitStrict && loadWaitBit, load will wait in rs until all older store addr calculation are finished. * chore: add storeset_load_strict_wait counter
-
- 09 9月, 2021 1 次提交
-
-
由 Yinan Xu 提交于
This commit adds some simple instruction fusion cases in decode stage. Currently we only implement instruction pairs that can be fused into RV64GCB instructions. Instruction fusions are detected in the decode stage by FusionDecoder. The decoder checks every two instructions and marks the first instruction fused if they can be fused into one instruction. The second instruction is removed by setting the valid field to false. Simple fusion cases include sh1add, sh2add, sh3add, sexth, zexth, etc. Currently, ftq in frontend needs every instruction to commit. However, the second instruction is removed from the pipeline and will not commit. To solve this issue, we temporarily add more bits to isFused to indicate the offset diff of the two fused instruction. There are four possibilities now. This feature may be removed later. This commit also adds more instruction fusion cases that need changes in both the decode stage and the funtion units. In this commit, we add some opcode to the function units and fuse the new instruction pairs into these new internal uops. The list of opcodes we add in this commit is shown below: - szewl1: `slli r1, r0, 32` + `srli r1, r0, 31` - szewl2: `slli r1, r0, 32` + `srli r1, r0, 30` - byte2: `srli r1, r0, 8` + `andi r1, r1, 255` - sh4add: `slli r1, r0, 4` + `add r1, r1, r2` - sr30add: `srli r1, r0, 30` + `add r1, r1, r2` - sr31add: `srli r1, r0, 31` + `add r1, r1, r2` - sr32add: `srli r1, r0, 32` + `add r1, r1, r2` - oddadd: `andi r1, r0, 1`` + `add r1, r1, r2` - oddaddw: `andi r1, r0, 1`` + `addw r1, r1, r2` - orh48: mask off the first 16 bits and or with another operand (`andi r1, r0, -256`` + `or r1, r1, r2`) Furthermore, this commit adds some complex instruction fusion cases to the decode stage and function units. The complex instruction fusion cases are detected after the instructions are decoded into uop and their CtrlSignals are used for instruction fusion detection. We add the following complex instruction fusion cases: - addwbyte: addw and mask it with 0xff (extract the first byte) - addwbit: addw and mask it with 0x1 (extract the first bit) - logiclsb: logic operation and mask it with 0x1 (extract the first bit) - mulw7: andi 127 and mulw instructions. Input to mul is AND with 0x7f if mulw7 bit is set to true.
-
- 24 7月, 2021 1 次提交
-
-
由 Yinan Xu 提交于
XiangShan is jointly released by ICT and PCL.
-
- 04 6月, 2021 1 次提交
-
-
由 Lemover 提交于
In this commit, we add License for XiangShan project.
-
- 11 5月, 2021 1 次提交
-
-
由 William Wang 提交于
* LoadQueue: send stFtqIdx via rollback request * It will make it possible for setore set to update its SSIT * StoreSet: setup store set update req * StoreSet: add store set identifier table (SSIT) * StoreSet: add last fetched store table (LFST) * StoreSet: put SSIT into decode stage * StoreSet: put LFST into dispatch1 * Future work: optimize timing * RS: store rs now supports delayed issue * StoreSet: add perf counter * StoreSet: fix SSIT update logic * StoreSet: delay LFST update input for 1 cycle * StoreSet: fix LFST update logic * StoreSet: fix LFST raddr width * StoreSet: do not force store in ss issue in order Classic store set requires store in the same store set issue in seq. However, in current micro-architecture, such restrict will lead to severe perf lost. We choose to disable it until we find another way to fix it. * StoreSet: support ooo store in the same store set * StoreSet: fix store set merge logic * StoreSet: check earlier store when read LFST * If store-load pair is in the same dispatch bundle, loadWaitBit should also be set for load * StoreSet: increase default SSIT flush period * StoreSet: fix LFST read logic * Fix commit c0e541d1 * StoreSet: add StoreSetEnable parameter * RSFeedback: add source type * StoreQueue: split store addr and store data * StoreQueue: update ls forward logic * Now it supports splited addr and data * Chore: force assign name for load/store unit * RS: add rs'support for store a-d split * StoreQueue: fix stlf logic * StoreQueue: fix addr wb sq update logic * AtomicsUnit: support splited a/d * Parameters: disable store set by default * WaitTable: wait table will not cause store delay * WaitTable: recover default reset period to 2^17 * Fix dev-stad merge conflict * StoreSet: enable storeset * RS: disable store rs delay logic CI perf shows that current delay logic will cause perf loss. Disable unnecessary delay logic will help. To be more specific, `io.readyVec` caused the problem. It will be updated in future commits. * RS: opt select logic with load delay (ldWait) * StoreSet: disable 2-bit lwt Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn>
-
- 19 4月, 2021 1 次提交
-
-
由 Jiawei Lin 提交于
* difftest: use DPI-C to refactor difftest In this commit, difftest is refactored with DPI-C calls. There're a few reasons: (1) From Verilator's manual, DPI-C calls should be more efficient than accessing from dut_ptr. (2) DPI-C is cross-platform (Verilator, VCS, ...) (3) difftest APIs are splited from emu.cpp to possibly support more backend platforms (NEMU, Spike, ...) The performance at this commit is quite slower than the original emu. Performance issues will be fixed later. * [WIP] SimTop: try to use 'XSTop' as soc * CircularQueuePtr: ues F-bounded polymorphis instead implict helper * Refactor parameters & Clean up code * difftest: support basic difftest * Support diffetst in new sim top * Difftest; convert recode fmt to ieee754 when comparing fp regs * Difftest: pass sign-ext pc to dpic functions && fix exception pc * Debug: add int/exc inst wb to debug queue * Difftest: pass sign-ext pc to dpic functions && fix exception pc * Difftest: fix naive commit num limit Co-authored-by: NYinan Xu <xuyinan1997@gmail.com> Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>
-
- 25 3月, 2021 1 次提交
-
-
由 Allen 提交于
XSPerfAccumulate: sum up performance values. XSPerfHistogram: count the occurrence of performance values, split them into bins, so that we can estimate their distribution. XSPerfMax: get max of performance values.
-
- 11 3月, 2021 1 次提交
-
-
由 Yinan Xu 提交于
-
- 08 3月, 2021 1 次提交
-
-
由 Yinan Xu 提交于
-
- 28 2月, 2021 1 次提交
-
-
由 William Wang 提交于
* WaitTable: add waittable framework * WaitTable: get replay info from RedirectGenerator * StoreQueue: maintain issuePtr for load rs * RS: add loadWait to rs (only for load Unit's rs) * WaitTable: fix update logic * StoreQueue: fix issuePtr update logic * chore: set loadWaitBit in ibuffer * StoreQueue: fix issuePtrExt update logic Former logic does not work well with mmio logic We may also make sure that issuePtrExt is not before cmtPtrExt * WaitTable: write with priority * StoreQueue: fix issuePtrExt update logic for mmio * chore: fix typos * CSR: add slvpredctrl * slvpredctrl will control load violation predict micro architecture * WaitTable: use xor folded pc to index waittable Co-authored-by: NZhangZifei <1773908404@qq.com>
-
- 21 1月, 2021 1 次提交
-
-
由 LinJiawei 提交于
-
- 16 1月, 2021 2 次提交
- 07 1月, 2021 1 次提交
-
-
由 Yinan Xu 提交于
-
- 11 12月, 2020 1 次提交
-
-
由 YikeZhou 提交于
-
- 01 12月, 2020 2 次提交
- 10 9月, 2020 1 次提交
-
-
由 Yinan Xu 提交于
-
- 02 8月, 2020 1 次提交
-
-
由 Lingrui98 提交于
-
- 31 7月, 2020 1 次提交
-
-
由 zhanglinjuan 提交于
-
- 28 7月, 2020 1 次提交
-
-
由 LinJiawei 提交于
-
- 16 7月, 2020 1 次提交
-
-
由 ZhangZifei 提交于
fix bug that DecodeStage could handle the sync between Brq and DecodeBuffer
-
- 14 7月, 2020 1 次提交
-
-
由 LinJiawei 提交于
-
- 12 7月, 2020 1 次提交
-
-
由 LinJiawei 提交于
-
- 04 7月, 2020 1 次提交
-
-
由 LinJiawei 提交于
-
- 26 6月, 2020 1 次提交
-
-
由 Yinan Xu 提交于
-
- 25 6月, 2020 2 次提交
- 24 6月, 2020 1 次提交
-
-
由 YikeZhou 提交于
-
- 22 6月, 2020 1 次提交
-
-
由 LinJiawei 提交于
-
- 18 6月, 2020 1 次提交
-
-
由 LinJiawei 提交于
-
- 16 6月, 2020 1 次提交
-
-
由 LinJiawei 提交于
-