backend: adaptive backend interface with frontend

src/main/scala/xiangshan/Bundle.scala

@@ -77,6 +77,7 @@ class Predecode extends XSBundle {
 class BranchUpdateInfo extends XSBundle {
   // from backend
   val pc = UInt(VAddrBits.W)
+  val pnpc = UInt(VAddrBits.W)
   val target = UInt(VAddrBits.W)
   val brTarget = UInt(VAddrBits.W)
   val taken = Bool()

src/main/scala/xiangshan/backend/brq/Brq.scala

@@ -237,10 +237,14 @@ class Brq extends XSModule {
   val fire = io.out.fire()
   val predRight = fire && !commitIsMisPred
   val predWrong = fire && commitIsMisPred
-  val isBType = commitEntry.exuOut.brUpdate.btbType===BTBtype.B
-  val isJType = commitEntry.exuOut.brUpdate.btbType===BTBtype.J
-  val isIType = commitEntry.exuOut.brUpdate.btbType===BTBtype.I
-  val isRType = commitEntry.exuOut.brUpdate.btbType===BTBtype.R
+  // val isBType = commitEntry.exuOut.brUpdate.btbType===BTBtype.B
+  val isBType = commitEntry.exuOut.brUpdate.pd.isBr
+  // val isJType = commitEntry.exuOut.brUpdate.btbType===BTBtype.J
+  val isJType = commitEntry.exuOut.brUpdate.pd.isJal
+  // val isIType = commitEntry.exuOut.brUpdate.btbType===BTBtype.I
+  val isIType = commitEntry.exuOut.brUpdate.pd.isJalr
+  // val isRType = commitEntry.exuOut.brUpdate.btbType===BTBtype.R
+  val isRType = commitEntry.exuOut.brUpdate.pd.isRet
   val mbpInstr = fire
   val mbpRight = predRight
   val mbpWrong = predWrong

src/main/scala/xiangshan/backend/decode/DecodeStage.scala

@@ -42,7 +42,7 @@ class DecodeStage extends XSModule {
     io.out(i).bits := decoderToDecBuffer(i)
 
     val thisReady = io.out(i).ready && io.toBrq(i).ready
-    val thisBrqValid = io.in(i).valid && decoders(i).io.out.cf.brUpdate.isBr && io.out(i).ready
+    val thisBrqValid = io.in(i).valid && decoders(i).io.out.cf.brUpdate.pd.isBr && io.out(i).ready
     val thisOutValid =  io.in(i).valid && io.toBrq(i).ready
     io.in(i).ready    := { if (i == 0) thisReady    else io.in(i-1).ready && thisReady }
     io.out(i).valid   := { if (i == 0) thisOutValid else io.in(i-1).ready && thisOutValid }

src/main/scala/xiangshan/backend/decode/Decoder.scala

@@ -24,10 +24,10 @@ class Decoder extends XSModule with HasInstrType {
   val instrType :: fuType :: fuOpType :: Nil = decodeList
 
   // todo: remove this when fetch stage can decide if an instr is br/jmp
-  io.out.cf.brUpdate.isBr := (instrType === InstrB ||
-                    (fuOpType === JumpOpType.jal && instrType === InstrJ && fuType === FuType.jmp) ||
-                    (fuOpType === JumpOpType.jalr && instrType === InstrI && fuType === FuType.jmp) ||
-                    (fuOpType === CSROpType.jmp && instrType === InstrI && fuType === FuType.csr))
+  // io.out.cf.brUpdate.isBr := (instrType === InstrB ||
+  //                   (fuOpType === JumpOpType.jal && instrType === InstrJ && fuType === FuType.jmp) ||
+  //                   (fuOpType === JumpOpType.jalr && instrType === InstrI && fuType === FuType.jmp) ||
+  //                   (fuOpType === CSROpType.jmp && instrType === InstrI && fuType === FuType.csr))
 //  val isRVC = instr(1, 0) =/= "b11".U
 //  val rvcImmType :: rvcSrc1Type :: rvcSrc2Type :: rvcDestType :: Nil =
 //    ListLookup(instr, CInstructions.DecodeDefault, CInstructions.CExtraDecodeTable)

src/main/scala/xiangshan/backend/exu/AluExeUnit.scala

@@ -52,7 +52,7 @@ class AluExeUnit extends Exu(Exu.aluExeUnitCfg) {
   val isJump = ALUOpType.isJump(func)
   val taken = LookupTree(ALUOpType.getBranchType(func), branchOpTable) ^ ALUOpType.isBranchInvert(func)
   val target = Mux(isBranch, pc + offset, adderRes)(VAddrBits-1,0)
-  val isRVC = uop.cf.brUpdate.isRVC//(io.in.bits.cf.instr(1,0) =/= "b11".U)
+  val isRVC = uop.cf.brUpdate.pd.isRVC//(io.in.bits.cf.instr(1,0) =/= "b11".U)
 
 
   io.in.ready := io.out.ready
@@ -65,14 +65,16 @@ class AluExeUnit extends Exu(Exu.aluExeUnitCfg) {
   io.out.bits.redirect.isException := false.B
   io.out.bits.redirect.isMisPred := DontCare // check this in brq
   io.out.bits.redirect.isReplay := false.B
-  io.out.bits.redirect.roqIdx := uop.roqIdx
+  // io.out.bits.redirect.roqIdx := uop.roqIdx
 
   io.out.bits.brUpdate := uop.cf.brUpdate
   // override brUpdate
+  io.out.bits.brUpdate.pc := uop.cf.pc
+  io.out.bits.brUpdate.target := Mux(!taken && isBranch, pcLatchSlot, target)
   io.out.bits.brUpdate.brTarget := target
-  io.out.bits.brUpdate.btbType := "b00".U
+  // io.out.bits.brUpdate.btbType := "b00".U
   io.out.bits.brUpdate.taken := isBranch && taken
-  io.out.bits.brUpdate.fetchIdx := uop.cf.brUpdate.fetchOffset >> 1.U  //TODO: consider RVC
+  // io.out.bits.brUpdate.fetchIdx := uop.cf.brUpdate.fetchOffset >> 1.U  //TODO: consider RVC
 
   io.out.valid := valid
   io.out.bits.uop <> io.in.bits.uop

src/main/scala/xiangshan/backend/fu/Jump.scala

@@ -16,7 +16,7 @@ class Jump extends FunctionUnit(jmpCfg){
   val redirectHit = uop.needFlush(io.redirect)
   val valid = iovalid && !redirectHit
 
-  val isRVC = uop.cf.brUpdate.isRVC
+  val isRVC = uop.cf.brUpdate.pd.isRVC
   val pcDelaySlot = Mux(isRVC, pc + 2.U, pc + 4.U)
   val target = src1 + offset // NOTE: src1 is (pc/rf(rs1)), src2 is (offset)
 
@@ -27,13 +27,15 @@ class Jump extends FunctionUnit(jmpCfg){
   io.out.bits.redirect.isException := false.B
   io.out.bits.redirect.isMisPred := DontCare // check this in brq
   io.out.bits.redirect.isReplay := false.B
-  io.out.bits.redirect.roqIdx := uop.roqIdx
+  // io.out.bits.redirect.roqIdx := uop.roqIdx
 
   io.out.bits.brUpdate := uop.cf.brUpdate
+  io.out.bits.brUpdate.pc := uop.cf.pc
+  io.out.bits.brUpdate.target := target
   io.out.bits.brUpdate.brTarget := target // DontCare
-  io.out.bits.brUpdate.btbType := LookupTree(func, RV32I_BRUInstr.bruFuncTobtbTypeTable)
+  // io.out.bits.brUpdate.btbType := LookupTree(func, RV32I_BRUInstr.bruFuncTobtbTypeTable)
   io.out.bits.brUpdate.taken := true.B
-  io.out.bits.brUpdate.fetchIdx := uop.cf.brUpdate.fetchOffset >> 1.U  //TODO: consider RVC
+  // io.out.bits.brUpdate.fetchIdx := uop.cf.brUpdate.fetchOffset >> 1.U  //TODO: consider RVC
 
   // Output
   val res = pcDelaySlot

src/main/scala/xiangshan/backend/roq/Roq.scala

@@ -196,7 +196,7 @@ class Roq(implicit val p: XSConfig) extends XSModule {
     (0 until CommitWidth).map(
       i => state === s_idle &&
         io.commits(i).valid &&
-        microOp(ringBufferTail+i.U).cf.brUpdate.isBr
+        microOp(ringBufferTail+i.U).cf.brUpdate.pd.isBr
     )
   ))
   io.bcommit := PopCount(validBcommit)

src/main/scala/xiangshan/frontend/BPU.scala

@@ -24,14 +24,14 @@ class TableAddr(val idxBits: Int, val banks: Int) extends XSBundle {
 class PredictorResponse extends XSBundle {
   class UbtbResp extends XSBundle {
   // the valid bits indicates whether a target is hit
-    val targets = Vec(PredictWidth, ValidUndirectioned(UInt(VaddrBits.W)))
+    val targets = Vec(PredictWidth, ValidUndirectioned(UInt(VAddrBits.W)))
     val takens = Vec(PredictWidth, Bool())
     val notTakens = Vec(PredictWidth, Bool())
     val isRVC = Vec(PredictWidth, Bool())
   }
   class BtbResp extends XSBundle {
   // the valid bits indicates whether a target is hit
-    val targets = Vec(PredictWidth, ValidUndirectioned(UInt(VaddrBits.W)))
+    val targets = Vec(PredictWidth, ValidUndirectioned(UInt(VAddrBits.W)))
     val types = Vec(PredictWidth, UInt(2.W))
     val isRVC = Vec(PredictWidth, Bool())
   }
@@ -81,7 +81,7 @@ class BPUStageIO extends XSBundle {
   val pc = UInt(VAddrBits.W)
   val mask = UInt(PredictWidth.W)
   val resp = new PredictorResponse
-  val target = UInt(VaddrBits.W)
+  val target = UInt(VAddrBits.W)
   val brInfo = Vec(PredictWidth, new BranchInfo)
 }
 
@@ -95,7 +95,7 @@ abstract class BPUStage extends XSModule {
   }
   def npc(pc: UInt, instCount: UInt) = pc + (instCount << 1.U)
 
-  io.in.ready = !outValid || io.out.fire() && io.pred.fire()
+  io.in.ready := !outValid || io.out.fire() && io.pred.fire()
   val inFire = io.in.fire()
   val inLatch = RegEnable(io.in.bits, inFire)
 

src/main/scala/xiangshan/frontend/Ibuffer.scala

@@ -68,7 +68,8 @@ class Ibuffer extends XSModule {
       io.out(i).bits.pc := ibuf(deq_idx).pc
       // io.out(i).bits.brUpdate := ibuf(deq_idx).brInfo
       io.out(i).bits.brUpdate := DontCare
-      io.out(i).bits.brUpdate.pc := io.out(i).bits.pc
+      io.out(i).bits.brUpdate.pc := ibuf(deq_idx).pc
+      io.out(i).bits.brUpdate.pnpc := ibuf(deq_idx).pnpc
       io.out(i).bits.brUpdate.pd := ibuf(deq_idx).pd
       io.out(i).bits.brUpdate.brInfo := ibuf(deq_idx).brInfo