debug: add debug log

src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala

@@ -5,7 +5,7 @@ import chisel3.util._
 import xiangshan._
 import xiangshan.utils._
 
-class DecodeBuffer extends XSModule with NeedImpl {
+class DecodeBuffer extends XSModule {
   val io = IO(new Bundle() {
     val redirect = Flipped(ValidIO(new Redirect))
     val in  = Vec(DecodeWidth, Flipped(DecoupledIO(new CfCtrl)))

src/main/scala/xiangshan/backend/decode/DecodeStage.scala

@@ -36,16 +36,16 @@ class DecodeStage extends XSModule {
     decoderToBrq(i) := decoders(i).io.out // CfCtrl without bfTag and brMask
     // send CfCtrl without brTags and brMasks to brq
     io.toBrq(i).valid := io.in(i).valid && io.out(i).ready && decoders(i).io.out.cf.isBr
-    XSDebug(io.toBrq(i).valid && io.toBrq(i).ready, p"Branch instr detected. Sending it to BRQ.")
-    XSDebug(io.toBrq(i).valid && !io.toBrq(i).ready, p"Branch instr detected. BRQ full...waiting")
-    XSDebug(io.in(i).valid && !io.out(i).ready, p"DecBuf full...waiting")
+    XSDebug(io.toBrq(i).valid && io.toBrq(i).ready, p"Branch instr detected. Sending it to BRQ.\n")
+    XSDebug(io.toBrq(i).valid && !io.toBrq(i).ready, p"Branch instr detected. BRQ full...waiting\n")
+    XSDebug(io.in(i).valid && !io.out(i).ready, p"DecBuf full...waiting\n")
     decoderToBrq(i).brMask := DontCare
     decoderToBrq(i).brTag := DontCare
     io.toBrq(i).bits := decoderToBrq(i)
     // if brq returns ready, then assert valid and send CfCtrl with bfTag and brMask to DecBuffer
     io.out(i).valid := io.toBrq(i).ready && io.in(i).valid
-    XSDebug(io.out(i).valid && decoders(i).io.out.cf.isBr && io.out(i).ready, p"Sending branch instr to DecBuf")
-    XSDebug(io.out(i).valid && !decoders(i).io.out.cf.isBr && io.out(i).ready, p"Sending non-branch instr to DecBuf")
+    XSDebug(io.out(i).valid && decoders(i).io.out.cf.isBr && io.out(i).ready, p"Sending branch instr to DecBuf\n")
+    XSDebug(io.out(i).valid && !decoders(i).io.out.cf.isBr && io.out(i).ready, p"Sending non-branch instr to DecBuf\n")
     decoderToDecBuffer(i) := decoders(i).io.out
     decoderToDecBuffer(i).brTag := io.brTags(i)
     decoderToDecBuffer(i).brMask := io.brMasks(i)

src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala

@@ -3,7 +3,7 @@ package xiangshan.backend.dispatch
 import chisel3._
 import chisel3.util._
 import xiangshan._
-import xiangshan.utils.{XSDebug, XSInfo}
+import xiangshan.utils.{XSDebug, XSInfo, XSWarn}
 
 case class DP1Config
 (
@@ -72,7 +72,7 @@ class Dispatch1 extends XSModule{
   for (i <- 0 until RenameWidth) {
     uop_nroq(i) := io.fromRename(i).bits
     uop_nroq(i).roqIdx := Mux(io.toRoq(i).ready, io.roqIdxs(i), roqIndexReg(i))
-    XSDebug(io.toRoq(i).fire(), "instruction 0x%x receives nroq %d\n", io.fromRename(i).bits.cf.pc, io.roqIdxs(i))
+
   }
 
   // uop can enqueue when rename.valid and roq.valid
@@ -93,6 +93,11 @@ class Dispatch1 extends XSModule{
   for (i <- 0 until RenameWidth) {
     io.toRoq(i).bits <> io.fromRename(i).bits
     io.toRoq(i).valid := io.fromRename(i).valid && !roqIndexRegValid(i)
+    XSDebug(io.toRoq(i).fire(), "instruction 0x%x receives nroq %d\n", io.fromRename(i).bits.cf.pc, io.roqIdxs(i))
+    if (i > 0) {
+      XSWarn(io.toRoq(i).fire() && !io.toRoq(i - 1).ready && io.toRoq(i - 1).valid,
+        "roq handshake not continuous %d", i.U)
+    }
     io.fromRename(i).ready := all_recv
     XSDebug(io.fromRename(i).valid, "instruction 0x%x of type %b is in %d-th slot\n",
       io.fromRename(i).bits.cf.pc, io.fromRename(i).bits.ctrl.fuType, i.U)

src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala

@@ -6,7 +6,7 @@ import xiangshan._
 import xiangshan.backend.regfile.RfReadPort
 import xiangshan.utils.{XSDebug, XSInfo}
 
-class Dispatch2 extends XSModule with NeedImpl {
+class Dispatch2 extends XSModule {
   val io = IO(new Bundle() {
     // from dispatch queues
     val fromIntDq = Flipped(Vec(IntDqDeqWidth, DecoupledIO(new MicroOp)))

src/main/scala/xiangshan/backend/exu/Exu.scala

@@ -108,11 +108,24 @@ trait HasExeUnits{
   exeUnits.foreach(_.io.dmem := DontCare)
 }
 
-class WriteBackArbMtoN(m: Int, n: Int) extends XSModule with NeedImpl {
+class WriteBackArbMtoN(m: Int, n: Int) extends XSModule {
   val io = IO(new Bundle() {
     val in = Vec(m, Flipped(DecoupledIO(new ExuOutput)))
     val out = Vec(n, ValidIO(new ExuOutput))
   })
+
+  // TODO: arbiter logic
+
+  for (i <- 0 until m) {
+    io.in(i).ready := false.B
+  }
+  io.out <> DontCare
+
+  for (i <- 0 until 4) {
+    io.out(i).valid := io.in(i+1).valid
+    io.out(i).bits := io.in(i+1).bits
+    io.in(i+1).ready := true.B
+  }
 }
 
 

src/main/scala/xiangshan/backend/issue/IssueQueue.scala

@@ -10,7 +10,7 @@ trait IQConst{
   val iqIdxWidth = log2Up(iqSize)
   val layer1Size = iqSize
   val layer2Size = iqSize/2
-  val debug = false
+  val debug = true
 }
 
 sealed abstract class IQBundle extends XSBundle with IQConst