Use fake Icache to fetch 8 instructions per cycle.

FPU can run at 200+MHz on axu3cg board now :)

[IntToFloat]: Count leading zeros of positive and negative number in parallel because IntToFloat is in the critical path

FPUv0.1 can pass all rvf/rvd tests in both riscv-tests and berkeley-softfloat
Signed-off-by: NLinJiawei <linjiav@outlook.com>

README.md: update doc

See merge request projectn/noop!77

Fpga

See merge request projectn/noop!76

Asic

See merge request projectn/noop!75

* refer to the RAS prediction hints in RV32I in the RISC-V manual

This reverts commit 2dfc501e.

Revert "Merge branch 'fix-mmio' into 'master'"

See merge request projectn/noop!73

This reverts merge request !72

noop: move the source of lsuMMIO from dcache to dtlb

See merge request projectn/noop!72

Fix debugfmt

See merge request projectn/noop!68

* if we disable dcache, the compilation will fail

device,AXI4Timer: add programmable freq and inc

See merge request projectn/noop!69

* This can help to generate desired frequency of timer interrupt, no
  matter what frequency of the clock is.

Debian

See merge request projectn/noop!66