Merge branch 'asic' into 'master'

Asic

See merge request projectn/noop!75

Makefile

@@ -58,6 +58,7 @@ VERILATOR_FLAGS = --top-module $(SIM_TOP) \
   +define+VERILATOR=1 \
   +define+PRINTF_COND=1 \
   +define+RANDOMIZE_REG_INIT \
+  +define+RANDOMIZE_MEM_INIT \
   --assert \
   --output-split 5000 \
   --output-split-cfuncs 5000 \
@@ -86,8 +87,10 @@ ifdef mainargs
 MAINARGS = -m $(mainargs)
 endif
 
+SEED = -s $(shell seq 1 10000 | shuf | head -n 1)
+
 emu: $(EMU)
-	@$(EMU) -i $(IMAGE) $(MAINARGS)
+	@$(EMU) -i $(IMAGE) $(SEED) $(MAINARGS)
 
 cache:
 	$(MAKE) emu IMAGE=Makefile

src/main/scala/noop/IDU2.scala

@@ -111,8 +111,12 @@ class IDU2(implicit val p: NOOPConfig) extends NOOPModule with HasInstrType {
   io.out.bits.data.imm  := Mux(isRVC, immrvc, imm)
 
   when (fuType === FuType.alu) {
-    when (rfDest === 1.U && fuOpType === ALUOpType.jal) { io.out.bits.ctrl.fuOpType := ALUOpType.call }
-    when (rfSrc1 === 1.U && fuOpType === ALUOpType.jalr) { io.out.bits.ctrl.fuOpType := ALUOpType.ret }
+    def isLink(reg: UInt) = (reg === 1.U || reg === 5.U)
+    when (isLink(rfDest) && fuOpType === ALUOpType.jal) { io.out.bits.ctrl.fuOpType := ALUOpType.call }
+    when (fuOpType === ALUOpType.jalr) {
+      when (isLink(rfSrc1)) { io.out.bits.ctrl.fuOpType := ALUOpType.ret }
+      when (isLink(rfDest)) { io.out.bits.ctrl.fuOpType := ALUOpType.call }
+    }
   }
   // fix LUI
   io.out.bits.ctrl.src1Type := Mux(instr(6,0) === "b0110111".U, SrcType.reg, src1Type)

src/main/scala/noop/TLB.scala

@@ -504,7 +504,7 @@ class TLBExec(implicit val tlbConfig: TLBConfig) extends TlbModule{
           val permExec = permCheck && missflag.x
           val permLoad = permCheck && (missflag.r || pf.status_mxr && missflag.x)
           val permStore = permCheck && missflag.w
-          val updateAD = false.B //!missflag.a || (!missflag.d && req.isWrite())
+          val updateAD = !missflag.a || (!missflag.d && req.isWrite())
           val updateData = Cat( 0.U(56.W), req.isWrite(), 1.U(1.W), 0.U(6.W) )
           missRefillFlag := Cat(req.isWrite(), 1.U(1.W), 0.U(6.W)) | missflag.asUInt
           memRespStore := io.mem.resp.bits.rdata | updateData 
@@ -606,4 +606,4 @@ object TLB {
     tlb.io.csrMMU <> csrMMU
     tlb
   }
-}
+}
\ No newline at end of file

src/main/scala/system/SoC.scala

@@ -3,6 +3,7 @@ package system
 import noop._
 import bus.axi4.{AXI4, AXI4Lite}
 import bus.simplebus._
+import device.AXI4Timer
 
 import chisel3._
 import chisel3.util._
@@ -28,7 +29,6 @@ class NOOPSoC(implicit val p: NOOPConfig) extends Module with HasSoCParameter {
     val mem = new AXI4
     val mmio = (if (p.FPGAPlatform) { new AXI4Lite } else { new SimpleBusUC })
     val frontend = Flipped(new AXI4)
-    val mtip = Input(Bool())
     val meip = Input(Bool())
     val ila = if (p.FPGAPlatform && EnableILA) Some(Output(new ILABundle)) else None
   })
@@ -70,10 +70,20 @@ class NOOPSoC(implicit val p: NOOPConfig) extends Module with HasSoCParameter {
   noop.io.imem.coh.req.valid := false.B
   noop.io.imem.coh.req.bits := DontCare
 
-  if (p.FPGAPlatform) io.mmio <> noop.io.mmio.toAXI4Lite()
-  else io.mmio <> noop.io.mmio
+  val addrSpace = List(
+    (0x40000000L, 0x08000000L), // external devices
+    (0x48000000L, 0x00010000L)  // CLINT
+  )
+  val mmioXbar = Module(new SimpleBusCrossbar1toN(addrSpace))
+  mmioXbar.io.in <> noop.io.mmio
 
-  val mtipSync = RegNext(RegNext(io.mtip))
+  val extDev = mmioXbar.io.out(0)
+  val clint = Module(new AXI4Timer(sim = !p.FPGAPlatform))
+  clint.io.in <> mmioXbar.io.out(1).toAXI4Lite()
+  if (p.FPGAPlatform) io.mmio <> extDev.toAXI4Lite()
+  else io.mmio <> extDev
+
+  val mtipSync = clint.io.extra.get.mtip
   val meipSync = RegNext(RegNext(io.meip))
   BoringUtils.addSource(mtipSync, "mtip")
   BoringUtils.addSource(meipSync, "meip")

src/test/csrc/main.cpp

@@ -42,8 +42,10 @@ std::vector<const char *> Emulator::parse_args(int argc, const char *argv[]) {
   while ( (o = getopt_long(argc, const_cast<char *const*>(argv), "-s:C:hi:m:", long_options, NULL)) != -1) {
     switch (o) {
       case 's': 
-        if(std::string(optarg) != "NO_SEED")
+        if(std::string(optarg) != "NO_SEED") {
           seed = atoll(optarg);
+          printf("Using seed = %d\n", seed);
+        }
         break;
       case 'C': max_cycles = atoll(optarg);  break;
       case 'i': image = optarg;

src/test/scala/top/NOOPSim.scala

@@ -47,7 +47,6 @@ class NOOPSimTop extends Module {
   mem.io.in <> memdelay.io.out
 
   mmio.io.rw <> soc.io.mmio
-  soc.io.mtip := mmio.io.mtip
 
   // soc.io.meip := Counter(true.B, 9973)._2  // use prime here to not overlapped by mtip
   soc.io.meip := false.B  // use prime here to not overlapped by mtip

src/test/scala/top/SimMMIO.scala

@@ -9,12 +9,10 @@ import device._
 class SimMMIO extends Module {
   val io = IO(new Bundle {
     val rw = Flipped(new SimpleBusUC)
-    val mtip = Output(Bool())
   })
 
   val devAddrSpace = List(
     (0x40600000L, 0x10L), // uart
-    (0x40700000L, 0x10000L), // timer
     (0x41000000L, 0x400000L), // vmem
     (0x40800000L, 0x8L),  // vga ctrl
     (0x40000000L, 0x1000L),  // flash
@@ -25,17 +23,13 @@ class SimMMIO extends Module {
   xbar.io.in <> io.rw
 
   val uart = Module(new AXI4UART)
-  val timer = Module(new AXI4Timer(sim = true))
   val vga = Module(new AXI4VGA(sim = true))
   val flash = Module(new AXI4Flash)
   val sd = Module(new AXI4DummySD)
   uart.io.in <> xbar.io.out(0).toAXI4Lite()
-  timer.io.in <> xbar.io.out(1).toAXI4Lite()
-  vga.io.in.fb <> xbar.io.out(2).toAXI4Lite()
-  vga.io.in.ctrl <> xbar.io.out(3).toAXI4Lite()
-  flash.io.in <> xbar.io.out(4).toAXI4Lite()
-  sd.io.in <> xbar.io.out(5).toAXI4Lite()
+  vga.io.in.fb <> xbar.io.out(1).toAXI4Lite()
+  vga.io.in.ctrl <> xbar.io.out(2).toAXI4Lite()
+  flash.io.in <> xbar.io.out(3).toAXI4Lite()
+  sd.io.in <> xbar.io.out(4).toAXI4Lite()
   vga.io.vga := DontCare
-
-  io.mtip := timer.io.extra.get.mtip
 }