- 15 1月, 2021 17 次提交
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由 Yinan Xu 提交于
L1 d cache fix bug
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由 ljw 提交于
Dispatch: palce ALUs after MDUs (Alu should be close to int regfile)
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由 Allen 提交于
See Tilelink spec 1.8.1 page 76. Section 9.3.5. ProbeAck and Section 9.3.5. ProbeAckData.
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由 Allen 提交于
conflict with prober with req_idx, not block_addr.
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由 LinJiawei 提交于
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由 LinJiawei 提交于
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由 Yinan Xu 提交于
Optimize imm and pc
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由 ljw 提交于
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由 Yinan Xu 提交于
misc: eliminate difftest signal in fpga mode
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由 LinJiawei 提交于
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由 LinJiawei 提交于
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由 wangkaifan 提交于
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由 Yinan Xu 提交于
datamodule template
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由 Yinan Xu 提交于
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由 ljw 提交于
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由 LinJiawei 提交于
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- 14 1月, 2021 23 次提交
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由 Yinan Xu 提交于
ci: add make verilog test
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 Yinan Xu 提交于
Trace debug
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由 ljw 提交于
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由 Yinan Xu 提交于
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由 Yinan Xu 提交于
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由 Yinan Xu 提交于
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由 Yinan Xu 提交于
CSR: add hardware performance counter framework
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由 Yinan Xu 提交于
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由 Yinan Xu 提交于
DCache: fixed sync bus between probe and LoadPipe, StorePipe and Atom…
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由 wangkaifan 提交于
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由 Allen 提交于
Now, every pipe directly carries the old_repl_meta to missQueue. So probe should block every pipe with same set req. In case they try to replace the block probe was manipulating. The buggy case happens this way: 1. Probe block A, which resides in set x, way y. 2. Probe has done almost everything except meta data update. 3. StorePipe handles block B, which missed in cache, so it try to replace set x, way y. Because Probe haven't update meta data, StorePipe gets a old copy of meta data, which means it will try to evict block A. 4. Probe finally update meta. 5. MissQueue accept miss request for block B from StorePipe, with the old_repl_meta, MissQueue tries to evict block A, although it's already probed out.
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由 Yinan Xu 提交于
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由 wangkaifan 提交于
* values of hardware performance counters can hardly be emulated by NEMU
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由 Yinan Xu 提交于
rs: remove buggy `if FPGAPlatform else ...` code
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由 LinJiawei 提交于
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由 YikeZhou 提交于
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由 LinJiawei 提交于
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由 Yinan Xu 提交于
LoadQueueData: use separate data module
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由 Yinan Xu 提交于
ci: add make verilog test ci: add make verilog test
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由 LinJiawei 提交于
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