and change rs data part's listen logic
when enq, if src from rf is not ready, the src will not be writen
  n data module
change enq listen src update logic, remote the highest bit of srcUpdate
which may be done later: enq listen will update srcQueue one cycle
  later

SRAMTemplate: support --infer-rw --repl-seq-mem

exu,div: set io.in.valid though the instruction is flushed

backend,busytable: update IOs and optimize timing

RS: timing optimizaton that rs enq listen to writeback other than busytable

RS: rs timing optimaziton and rename some signal && fence's timing optimization

L1plus : opt timing in valid_array read

backend,roq: RegNext isEmpty and block commits when exceptions for better timing

excitingutils: warn wires that have multiple sink|source

Icache uncache

csr: support privMode check for perfcnt regs

opt fdiv timing

roq: optimize commit timing and block commits when exceptions occur

For single port SRAM icache, we disable read when write. So we disable
if1_cango when flush if2 register

to not pass fu.ready to dispatch through rs

idx      -> index
red      -> redirect
fb       -> feedback
iss      -> issue
sel      -> select
bub      -> bubble
cnt      -> count
wu       -> wakeup
bp       -> bypass

excitingutils: fix typo and enhance multiple wiring check

L1plusCache: change SRAM spec.

Use DontCare to remove L2 inner A channel's data field.

LoadQueueData: use sync read

StoreQueue: read sbuffer data 1 cycle earlier