- 28 6月, 2022 1 次提交
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由 William Wang 提交于
This commit re-pipelines ECC check logic in data cache and exception generate logic for better timing. Now ecc error is checked 1 cycle after reading result from data sram. An extra cycle is added for load writeback to ROB. Future work: move the pipeline to https://github.com/OpenXiangShan/XiangShan/blob/master/src/main/scala/xiangshan/backend/CtrlBlock.scala#L266-L277, which add a regnext. * dcache: repipeline ecc check logic for timing * chore: fix normal loadAccessFault logic * wbu: delay load unit wb for 1 cycle * dcache: add 1 extra cycle for beu error report
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- 09 5月, 2022 1 次提交
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由 Jenius 提交于
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- 07 5月, 2022 1 次提交
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由 Guokai Chen 提交于
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- 06 5月, 2022 1 次提交
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由 Haojin Tang 提交于
* feat: parameterize load/store pipeline, etc. * fix: use LoadPipelineWidth rather than LoadQueueSize * fix: parameterize `rdataPtrExtNext` * SBuffer: fix idx update logic * atomic: parameterize atomic logic in `MemBlock` * StoreQueue: update allow enque requirement * feat: support one load/store pipeline * feat: parameterize `EnsbufferWidth` * chore: resharp codes for better generated name
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- 04 5月, 2022 1 次提交
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由 Yinan Xu 提交于
This commit fixes the implementation of WFI. The WFI instruction waits in the ROB until an interrupt might need servicing. According to the RISC-V manual, the WFI must be unaffected by the global interrupt bits in `mstatus` and the delegation register `mideleg`.
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- 28 4月, 2022 1 次提交
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由 Yinan Xu 提交于
The RISC-V WFI instruction is previously decoded as NOP. This commit adds support for the real wait-for-interrupt (WFI). We add a state_wfi FSM in the ROB. After WFI leaves the ROB, the next instruction will wait in the ROB until an interrupt.
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- 14 4月, 2022 1 次提交
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由 Lemover 提交于
old missqueue: cache req miss slot and mem access-er Problem: these two func are totally different, make mq hard to handle in a single select policy. Solution: divide these two funciton into two module. new MissQueue: only hold reqs that page cache miss and need re-req cache, a simple flushable queue llptw: Last level ptw, only access ptes, priorityMux queue * mmu: rename PTW.scala to L2TLB.scala * mmu: rename PTW to L2TLB * mmu: rename PtwFsm to PTW * mmu.l2tlb: divide missqueue into 'missqueue' and llptw old missqueue: cache req miss slot and mem access-er Problem: these two func are totally different, make mq hard to handle in single select policy. Solution: divide these two funciton into two module. new MissQueue: only hold reqs that page cache miss and new re-req cache llptw: Last level ptw, only access ptes * mmu.l2tlb: syntax bug that misses io assign * mmu.l2tlb: fix bug that mistakes ptw's block signal
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- 28 1月, 2022 1 次提交
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由 Jiawei Lin 提交于
* Adjusted reset signals * Support reset tree
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- 01 1月, 2022 1 次提交
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由 William Wang 提交于
* mem: fix error csr update * dcache: l2 error will now trigger atom error * chore: fix cache error debug decoder * mem: split L1CacheErrorInfo and L1BusErrorUnitInfo
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- 21 12月, 2021 1 次提交
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由 Yinan Xu 提交于
This commit adds an LsqEnqCtrl module to add one more clock cycle between dispatch and load/store queue. LsqEnqCtrl maintains the lqEnqPtr/sqEnqPtr and lqCounter/sqCounter. They are used to determine whether load/store queue can accept new instructions. After that, instructions are sent to load/store queue. This module decouples queue allocation and real enqueue. Besides, uop storage in load/store queue are optimized. In dispatch, only robIdx is required. Other information is naturally conveyed in the pipeline and can be stored later in load/store queue if needed. For example, exception vector, trigger, ftqIdx, pdest, etc are unnecessary before the instruction leaves the load/store pipeline.
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- 10 12月, 2021 2 次提交
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由 William Wang 提交于
* mem,cacheop: fix read data writeback * mem,cacheop: rename cacheop state bits These bits are different from w_*, s_* bits in cache * mem: enable icache op feedback * icache: update cache op implementation * chore: remove cache op logic from XSCore.scala
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由 Yinan Xu 提交于
This commit optimizes the coding style and timing for hardware performance counters. By default, performance counters are RegNext(RegNext(_)).
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- 09 12月, 2021 1 次提交
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由 Yinan Xu 提交于
This commit adds WritebackSink and WritebackSource parameters for multiple modules. These traits hide implementation details from other modules by defining IO-related functions in modules. By using WritebackSink, ROB is able to choose the writeback sources. Now fflags and exceptions are connected from exe units to reduce write ports and optimize timing. Further optimizations on write-back to RS and better coding style to be added later.
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- 06 12月, 2021 1 次提交
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由 Jiawei Lin 提交于
* SoC: add axi4spliter * pmp: add apply method to reduce loc * pma: add PMA used in axi4's spliter * Fix package import * pma: re-write tl-pma, put tl-pma into AXI4Spliter * pma: add memory mapped pma * soc: rm dma port, rm axi4spliter, mv mmpma out of spliter * Remove unused files * update dma pma check port at SimTop.scala; update pll lock defalt value to 1 Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn> Co-authored-by: Nrvcoresjw <shangjiawei@rvcore.com>
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- 05 12月, 2021 1 次提交
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由 Yinan Xu 提交于
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- 01 12月, 2021 1 次提交
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由 Yinan Xu 提交于
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- 16 11月, 2021 1 次提交
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由 Jiawei Lin 提交于
* FDivSqrt: use hierarchy API to avoid dedup bug * Dedup: use hartId from io port instead of core parameters * Bump fudian
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- 12 11月, 2021 2 次提交
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由 Yinan Xu 提交于
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由 ZhangZifei 提交于
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- 11 11月, 2021 1 次提交
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由 Yinan Xu 提交于
* disable log as default * code clean up
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- 07 11月, 2021 1 次提交
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由 Yinan Xu 提交于
This fixes differences between the pingpong bits in ctrlblock and dispatch2.
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- 05 11月, 2021 1 次提交
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由 Yinan Xu 提交于
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- 30 10月, 2021 1 次提交
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由 Yinan Xu 提交于
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- 27 10月, 2021 1 次提交
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由 Lemover 提交于
* l2tlb: add repeater/filter's object apply method * l2tlb: add one more cycle(repeater) between itlb and l2tlb
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- 24 10月, 2021 1 次提交
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由 Yinan Xu 提交于
This commit changes when instructions enter load/store queue. Now, at dispatch2, load/store instructions enter load/store queue.
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- 23 10月, 2021 1 次提交
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由 rvcoresjw 提交于
* Add perf counters * add reg from hpm counter source * add print perfcounter enable
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- 22 10月, 2021 3 次提交
- 21 10月, 2021 2 次提交
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由 William Wang 提交于
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由 happy-lx 提交于
add mmu's asid support. 1. put asid inside sram (if the entry is sram), or it will take too many sources. 2. when sfence, just flush it all, don't care asid. 3. when hit check, check asid. 4. when asid changed, flush all the inflight ptw req for safety 5. simple asid unit test: asid 1 write, asid 2 read and check, asid 2 write, asid 1 read and check. same va, different pa * ASID: make satp's asid bits configurable to RW * use AsidLength to control it * ASID: implement asid refilling and hit checking * TODO: sfence flush with asid * ASID: implement sfence with asid * TODO: extract asid from SRAMTemplate * ASID: extract asid from SRAMTemplate * all is down * TODO: test * fix write to asid * Sfence: support rs2 of sfence and fix Fence Unit * rs2 of Sfence should be Reg and pass it to Fence Unit * judge the value of reg instead of the index in Fence Unit * mmu: re-write asid now, asid is stored inside sram, so sfence just flush it it's a complex job to handle the problem that asid is changed but no sfence.vma is executed. when asid is changed, all the inflight mmu reqs are flushed but entries in storage is not influenced. so the inflight reqs do not need to record asid, just use satp.asid * tlb: fix bug of refill mask * ci: add asid unit test Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn>
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- 16 10月, 2021 1 次提交
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由 Yinan Xu 提交于
This commit removes flush IO for every module. Flush now re-uses redirect ports to flush the instructions.
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- 14 10月, 2021 1 次提交
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由 Lemover 提交于
预取时机: 或者 发生miss时 或者 发生hit,但是hit的entry是预取上来的 当 页表2MB的level命中 当 预取项不跨2MB项对应的4KB page frame 前面两个限制是为了限制预取的数量 后面两个限制是限制预取请求只会访问最后一级页表 -› 不占用FSM & (几乎)不会重新访问cache,造成卡死。 ============= some workloads: gcc(5.4%), wrf(13.6%),milc(9.2%)'s ipc increase. some workloads decrease: namd(-2.5%). but l2tlb's perf counters are better. So I think it is worthy to adding the simple next-line prefetch. The workloads are of ci and in cold-start state, so prefetch may seems to be much better than it should be. But l2tlb's memory access ability is much better than what it needs, so the prefetch can be added. ============= * mmu.l2tlb: add params filterSize * mmu.l2tlb: add prefetch,dont work well * mmu.l2tlb: add prefetch relative perf counter * l2tlb: prefetch recv miss req and 'hit but pre-fetched' req * l2tlb: fix some perf counter about prefetch * l2tlb: prefetch not cross 2MB && not recv when 2MB level miss * ci: when error, copy emu and SimTop.v to WAVE_HOME
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- 13 10月, 2021 1 次提交
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由 Jiawei Lin 提交于
* Temporarily disable TLMonitor * Bump huancun (L2/L3 MSHR bug fix) * Refactor Top * Bump huancun * alu: fix bug of rev8 & orc.b instruction Co-authored-by: Zhangfw <471348957@qq.com>
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- 12 10月, 2021 3 次提交
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由 Yinan Xu 提交于
This commit adds IOs for performance counters in reservation stations. Only `full` is included for now.
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由 William Wang 提交于
* mem: update block load logic Now load will be selected as soon as the store it depends on is ready, which is predicted by Store Sets * mem: opt block load logic Load blocked by std invalid will wait for that std to issue Load blocked by load violation wait for that sta to issue * csr: add 2 extra storeset config bits Following bits were added to slvpredctl: - storeset_wait_store - storeset_no_fast_wakeup * storeset: fix waitForSqIdx generate logic Now right waitForSqIdx will be generated for earlier store in the same dispatch bundle
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由 Yinan Xu 提交于
This commit changes how dispatch ports (regfile ports) are connected to reservation station ports: INT regfile: * INT(0-1) --> ALU0, MUL0, JUMP * INT(2-3) --> ALU1, MUL0 * INT(4-5) --> ALU2, MUL1 * INT(6-7) --> ALU3, MUL1 * INT(8) --> LOAD0 * INT(9) --> LOAD1 * INT(10) --> STA0 * INT(11) --> STA1 * INT(12) --> STD0 * INT(13) --> STD1 FP regfile: * FP(0-2) --> FMA0, FMISC0 * FP(3-5) --> FMA1, FMISC0 * FP(6-8) --> FMA2, FMISC1 * FP(9-11) --> FMA3, FMISC1 * FP(12) --> STD0 * FP(13) --> STD1
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- 11 10月, 2021 2 次提交
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由 Lemover 提交于
* [WIP] PMP: add pmp to tlb & csr(ptw part is not added) * pmp: add pmp, unified * pmp: add pmp, distributed but same cycle * pmp: pmp resp next cycle * [WIP] PMP: add l2tlb missqueue pmp support * pmp: add pmp to ptw and regnext pmp for frontend * pmp: fix bug of napot-match * pmp: fix bug of method aligned * pmp: when write cfg, update mask * pmp: fix bug of store af getting in store unit * tlb: fix bug, add af check(access fault from ptw) * tlb: af may have higher priority than pf when ptw has af * ptw: fix bug of sending paddr to pmp and recv af * ci: add pmp unit test * pmp: change PMPPlatformGrain to 6 (512bits) * pmp: fix bug of read_addr * ci: re-add pmp unit test * l2tlb: lazymodule couldn't use @chiselName * l2tlb: fix bug of l2tlb missqueue duplicate req's logic filt the duplicate req: old: when enq, change enq state to different state new: enq + mem.req.fire, more robust * pmp: pmp checker now supports samecycle & regenable
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由 William Wang 提交于
Make bank conflict feedback 1 cycle earlier
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- 10 10月, 2021 1 次提交
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由 Yinan Xu 提交于
FastUops from ExuBlock contain some outside function units, which should be removed.
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