Adjusted reset signals (#1441)

* Adjusted reset signals

* Support reset tree

huancun @ 3df11606

-Subproject commit f985e61b162ed4d0ed61f56dae2dc0cf8c79b7d2
+Subproject commit 3df11606fa9243308802b829a0ea6434eb51fd61

src/main/scala/top/Configs.scala

@@ -231,7 +231,8 @@ class WithNKBL2
         enablePerf = true,
         sramDepthDiv = 2,
         tagECC = Some("secded"),
-        dataECC = Some("secded")
+        dataECC = Some("secded"),
+        simulation = !site(DebugOptionsKey).FPGAPlatform
       )),
       L2NBanks = banks
     ))
@@ -264,7 +265,8 @@ class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1
         sramClkDivBy2 = true,
         sramDepthDiv = 4,
         tagECC = Some("secded"),
-        dataECC = Some("secded")
+        dataECC = Some("secded"),
+        simulation = !site(DebugOptionsKey).FPGAPlatform
       ))
     )
 })

src/main/scala/top/Top.scala

@@ -191,12 +191,8 @@ class XSTop()(implicit p: Parameters) extends BaseXSSoc() with HasSoCParameter
 
     withClockAndReset(io.clock.asClock, io.reset) {
       // Modules are reset one by one
-      // reset ----> SYNC --> {L3 Cache, Cores}
-      //         |
-      //         v
-      //        misc
-      val l3cacheMod = if (l3cacheOpt.isDefined) Seq(l3cacheOpt.get.module) else Seq()
-      val resetChain = Seq(l3cacheMod ++ core_with_l2.map(_.module))
+      // reset ----> SYNC --> {SoCMisc, L3 Cache, Cores}
+      val resetChain = Seq(Seq(misc.module) ++ l3cacheOpt.map(_.module) ++ core_with_l2.map(_.module))
       ResetGen(resetChain, io.reset, !debugOpts.FPGAPlatform)
     }
 

src/main/scala/utils/ResetGen.scala

@@ -27,7 +27,30 @@ class ResetGen extends Module {
   io.out := RegNext(RegNext(reset.asBool))
 }
 
+trait ResetNode
+
+case class ModuleNode(mod: MultiIOModule) extends ResetNode
+
+case class ResetGenNode(children: Seq[ResetNode]) extends ResetNode
+
 object ResetGen {
+
+  def apply(resetTree: ResetNode, reset: Bool, sim: Boolean): Unit = {
+    if(!sim) {
+      resetTree match {
+        case ModuleNode(mod) =>
+          mod.reset := reset
+        case ResetGenNode(children) =>
+          val next_rst = Wire(Bool())
+          withReset(reset){
+            val resetGen = Module(new ResetGen)
+            next_rst := resetGen.io.out
+          }
+          children.foreach(child => apply(child, next_rst, sim))
+      }
+    }
+  }
+
   def apply(resetChain: Seq[Seq[MultiIOModule]], reset: Bool, sim: Boolean): Seq[Bool] = {
     val resetReg = Wire(Vec(resetChain.length + 1, Bool()))
     resetReg.foreach(_ := reset)

src/main/scala/xiangshan/XSCore.scala

@@ -23,6 +23,7 @@ import chisel3.util._
 import freechips.rocketchip.diplomacy.{BundleBridgeSource, LazyModule, LazyModuleImp}
 import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple}
 import freechips.rocketchip.tile.HasFPUParameters
+import freechips.rocketchip.tilelink.TLBuffer
 import system.HasSoCParameter
 import utils._
 import xiangshan.backend._
@@ -138,8 +139,11 @@ abstract class XSCoreBase()(implicit p: config.Parameters) extends LazyModule
   // outer facing nodes
   val frontend = LazyModule(new Frontend())
   val ptw = LazyModule(new PTWWrapper())
+  val ptw_to_l2_buffer = LazyModule(new TLBuffer)
   val csrOut = BundleBridgeSource(Some(() => new DistributedCSRIO()))
 
+  ptw_to_l2_buffer.node := ptw.node
+
   val wbArbiter = LazyModule(new WbArbiterWrapper(exuConfigs, NRIntWritePorts, NRFpWritePorts))
   val intWbPorts = wbArbiter.intWbPorts
   val fpWbPorts = wbArbiter.fpWbPorts
@@ -251,6 +255,7 @@ class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer)
   val wb2Ctrl = outer.wb2Ctrl.module
   val memBlock = outer.memBlock.module
   val ptw = outer.ptw.module
+  val ptw_to_l2_buffer = outer.ptw_to_l2_buffer.module
   val exuBlocks = outer.exuBlocks.map(_.module)
 
   ctrlBlock.io.hartId := io.hartId
@@ -397,18 +402,30 @@ class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer)
   io.l2_pf_enable := csrioIn.customCtrl.l2_pf_enable
 
   // Modules are reset one by one
-  // reset --> SYNC ----> SYNC ------> SYNC -----> SYNC -----> SYNC ---
-  //                  |          |            |           |           |
-  //                  v          v            v           v           v
-  //                 PTW  {MemBlock, dtlb}  ExuBlocks  CtrlBlock  {Frontend, itlb}
-  val resetChain = Seq(
-    Seq(memBlock, dtlbRepeater1, dtlbRepeater2),
-    Seq(exuBlocks.head),
-    // Note: arbiters don't actually have reset ports
-    exuBlocks.tail ++ Seq(outer.wbArbiter.module),
-    Seq(ctrlBlock),
-    Seq(ptw),
-    Seq(frontend, itlbRepeater1, itlbRepeater2)
+  val resetTree = ResetGenNode(
+    Seq(
+      ModuleNode(memBlock), ModuleNode(dtlbRepeater1),
+      ResetGenNode(Seq(
+        ModuleNode(itlbRepeater2),
+        ModuleNode(ptw),
+        ModuleNode(dtlbRepeater2),
+        ModuleNode(ptw_to_l2_buffer),
+      )),
+      ResetGenNode(Seq(
+        ModuleNode(exuBlocks.head),
+        ResetGenNode(
+          exuBlocks.tail.map(m => ModuleNode(m)) :+ ModuleNode(outer.wbArbiter.module)
+        ),
+        ResetGenNode(Seq(
+          ModuleNode(ctrlBlock),
+          ResetGenNode(Seq(
+            ModuleNode(frontend), ModuleNode(itlbRepeater1)
+          ))
+        ))
+      ))
+    )
   )
-  ResetGen(resetChain, reset.asBool, !debugOpts.FPGAPlatform)
+
+  ResetGen(resetTree, reset.asBool, !debugOpts.FPGAPlatform)
+
 }

src/main/scala/xiangshan/XSTile.scala

@@ -94,22 +94,27 @@ class XSTile()(implicit p: Parameters) extends LazyModule
   val beu_int_source = misc.beu.intNode
   val core_reset_sink = BundleBridgeSink(Some(() => Bool()))
 
-  if (coreParams.dcacheParametersOpt.nonEmpty) {
-    misc.l1d_logger :=
-      TLBuffer.chainNode(1, Some("L1D_to_L2_buffer")) :=
-      core.memBlock.dcache.clientNode
+  val l1d_to_l2_bufferOpt = coreParams.dcacheParametersOpt.map { _ =>
+    val buffer = LazyModule(new TLBuffer)
+    misc.l1d_logger := buffer.node := core.memBlock.dcache.clientNode
+    buffer
   }
+
+  val l1i_to_l2_buffer = LazyModule(new TLBuffer)
   misc.busPMU :=
     TLLogger(s"L2_L1I_${coreParams.HartId}", !debugOpts.FPGAPlatform) :=
-    TLBuffer.chainNode(1, Some("L1I_to_L2_buffer")) :=
+    l1i_to_l2_buffer.node :=
     core.frontend.icache.clientNode
 
-  if (!coreParams.softPTW) {
+  val ptw_to_l2_bufferOpt = if (!coreParams.softPTW) {
+    val buffer = LazyModule(new TLBuffer)
     misc.busPMU :=
       TLLogger(s"L2_PTW_${coreParams.HartId}", !debugOpts.FPGAPlatform) :=
-      TLBuffer.chainNode(3, Some("PTW_to_L2_buffer")) :=
-      core.ptw.node
-  }
+      buffer.node :=
+      core.ptw_to_l2_buffer.node
+    Some(buffer)
+  } else None
+
   l2cache match {
     case Some(l2) =>
       misc.l2_binder.get :*= l2.node :*= TLBuffer() :*= misc.l1_xbar
@@ -150,9 +155,10 @@ class XSTile()(implicit p: Parameters) extends LazyModule
     //             |
     //             v
     // reset ----> OR_SYNC --> {Misc, L2 Cache, Cores}
-    val l2cacheMod = if (l2cache.isDefined) Seq(l2cache.get.module) else Seq()
     val resetChain = Seq(
-      Seq(misc.module, core.module) ++ l2cacheMod
+      Seq(misc.module, core.module, l1i_to_l2_buffer.module) ++
+        l2cache.map(_.module) ++
+        l1d_to_l2_bufferOpt.map(_.module) ++ ptw_to_l2_bufferOpt.map(_.module)
     )
     ResetGen(resetChain, reset.asBool || core_soft_rst, !debugOpts.FPGAPlatform)
   }