* mmu: wrap l2tlb's param withL2TLBParameters

* mmu.l2tlb: add param blockBytes: 64, 8 ptes

* mmu.l2tlb: set l2tlb cache size to l2:256, l3:4096

* mmu.l2tlb: add config print

* mmu.l2tlb: fix bug of resp data indices choosen and opt coding style

This reverts commit 5aae5b8d.

* Miniconfig: change dtlb size to 32 at minimal config

* mmu.dtlb: change tlb's replacement access code style

dtlb now can support plru (functionaly).
plru with multi-access is chained, so there will be long latency
  for dtlb to use plru.

* mmu.tlb: add tlb at new level named btlb

bridge tlb:
one l0-tlb in each mem pipeline
all the l0-tlb connect to bridge tlb
btlb connects to l2tlb, so btlb is also l1-tlb
itlb remains the same

* mmu.tlb: set tlb size: l0-8, l1-64

* mmu.btlb: add sfence logic

* mmu.tlb: fix bug of sfence logic of g bit

* mmu.btlb: add some perf counter

* mmu.btlb: fix bug of random replace

* mmu.filter: add port vector to record which ports the reqs come from

* mmu.btlb: add some perf counter && add refill mask

* mmu.filter: add check for flushed req

This commit separates store address and store data in backend, including both reservation stations and function units. This commit also changes how stIssuePtr is updated. stIssuePtr should only be updated when both store data and address issue. 

* Miniconfig: change dtlb size to 32 at minimal config

* mmu.dtlb: change tlb's replacement access code style

dtlb now can support plru (functionaly).
plru with multi-access is chained, so there will be long latency
  for dtlb to use plru.

* mmu.l2tlb: cut down l2tlb.l2 to 256 and set l3.way to 8

* mmu.l2tlb: cut down l2tlb.l3 to 2048 from 4096

* Revert "mmu.l2tlb: cut down l2tlb.l3 to 2048 from 4096"

This reverts commit efbb077ef4be1d4e585a49537ba9be3144423b52.

Basic features of debug mode are implemented.

* Rewrite CSR for debug mode
* Peripheral work for implementing debug module
* Added single step support
* Use difftest with JTAG support

tage: fix phist support

Backend --> ExuBlock --> FuBlock --> Exu --> Function Units
        -->          --> Scheduler --> RS

Add Tage into Composer
Add global history manage logic in BPU
Modify CfiUpdate interface: sawNotTakenBranch -> br_hit

Fix Bim read idx bug
Remove valids in BranchPredictionResp
Modify out from Decoupled to Output in BasePredictorIO

XiangShan is jointly released by ICT and PCL.

This commit adds support for a parameterized scheduler. A scheduler
can be parameterized via issue and dispatch ports.

Note: other parameters have not been tested.

* PTW: Repeater support multi req by RRArbiter

* ptw: add parameter to choose repeater and filter(default)

simple ci test show that: the filter is critical for perf
like mcf(5m):
  old ptw:2.38
  new ptw with repeater: 2.41
  new ptw with filter: 2.58

This commit adds support for a parameterized scheduler. A scheduler
can be parameterized via issue and dispatch ports.

Note: other parameters have not been tested.

* Now can pass compiling.

[WIP] comment out-of-date code in frontend

[WIP] move NewFtq to xiangshan.frontend and rename class to Ftq

Ibuffer: update sigal names for new IFU

[WIP] remove redundant NewFrontend

[WIP] set entry_fetch_status to f_sent once send req to buf

Fix syntax error in IFU

Fix syntax error in IFU/ICache/Ibuffer

[WIP] indent fix in ftq

BPU: Move GlobalHistory define from IFU.scala to BPU.scala

[WIP] fix some compilation errors

BPU: Remove HasIFUConst
and move some bundles from BPU.scala to frontendBundle.scala

[WIP] fix some compilation errors

[WIP] rename ftq-bpu ios

[WIP] recover some const definitions

[WIP] fix some compilation errors

[WIP]connect some IOs in frontend

BPU: fix syntax error

[WIP] fix compilation errors in predecode

BPU: fix RAS syntax error

[WIP] add some simulation perf counters back

BPU: Remove numBr redefine in ubtb and bim

add handshake between pipeline stage

* PTW: Repeater support multi req by RRArbiter

* ptw: add parameter to choose repeater and filter(default)

simple ci test show that: the filter is critical for perf
like mcf(5m):
  old ptw:2.38
  new ptw with repeater: 2.41
  new ptw with filter: 2.58

In this commit, we add License for XiangShan project. 

* PTW: add ptw multi-processing graph

* [WIP] PTW: try to add miss queue, failed for complexity and not very useful

* [WIP] PTW: rewrite ptw for multi req support

* PTW: remove some assert, fix level init bug

* PTW: itlb has highter priority than dtlb

* PTW: fix bug that mix cache's resp logic

* PTW: fix stupid bug that mix .U and .W

* PTW: replay will not be blocked if fsm empty

* PTW: miss queue req may return miss queue

In the before design, only miss queue req can go into
fsm, and would not be blocked.
Now, to simplify design, miss queue req are just the
same with new req, may blocked, going to fsm or miss queue.

* PTW: fix ptw filter iss valid bug

* PTW.fsm: fix bug that should not mem.req when sfenceLatch

* PTW: fix ptw sfenceLatch's bug

* PTW: add some perf counters

* PTW: fix bug in filter enq ptr logic

* PTW: fix bug of sfence in ptw

* test: add current branch to ci-test, tmp

* PTW: fix bug of cache's hit logic and fsm's pf

* PTW: fix bug of filter's enq and block* signal

* PTW: fix bug of filter's pteResp filter

* PTW: add some assert of filter's counter

* PTW: fix bug of filter's enq logic

* PTW: set PTWMSHRSIZE 16

* PTW: fix naive perf counter's bug

* PTW: set PTWMSHRSIZE 8

* PTW: set PTWMSHRSIZE 32

* Revert "PTW: set PTWMSHRSIZE 32"

This reverts commit fd3981ae8bbb015c6cd398c4db60486d39fc92ef.

* Revert "test: add current branch to ci-test, tmp"

This reverts commit 8a7a8a494d5c05789e05a385a9fc7791a8ffef2f.

* Configs: add MinimalFPGAConfig

* TODO: change cache parameters

* Chore: add parameter print

* README: add simulation usage

Currently, XiangShan does not support NOOP FPGA. FPGA related
instructions are removed

* Configs: limit frontend width in MinimalConfig

* MinimalConfig: limit L1/L2 cache size

* MinimalConfig: limit ptw size, disable L2

* MinimalConfig: limit L3 size

* Sbuffer: force trigger write if sbuffer fulls

* LoadQueue: send stFtqIdx via rollback request

* It will make it possible for setore set to update its SSIT

* StoreSet: setup store set update req

* StoreSet: add store set identifier table (SSIT)

* StoreSet: add last fetched store table (LFST)

* StoreSet: put SSIT into decode stage

* StoreSet: put LFST into dispatch1

* Future work: optimize timing

* RS: store rs now supports delayed issue

* StoreSet: add perf counter

* StoreSet: fix SSIT update logic

* StoreSet: delay LFST update input for 1 cycle

* StoreSet: fix LFST update logic

* StoreSet: fix LFST raddr width

* StoreSet: do not force store in ss issue in order

Classic store set requires store in the same store set issue in seq.
However, in current micro-architecture, such restrict will lead to
severe perf lost. We choose to disable it until we find another way
to fix it.

* StoreSet: support ooo store in the same store set

* StoreSet: fix store set merge logic

* StoreSet: check earlier store when read LFST

* If store-load pair is in the same dispatch bundle, loadWaitBit should
also be set for load

* StoreSet: increase default SSIT flush period

* StoreSet: fix LFST read logic

* Fix commit c0e541d1

* StoreSet: add StoreSetEnable parameter

* RSFeedback: add source type

* StoreQueue: split store addr and store data

* StoreQueue: update ls forward logic

* Now it supports splited addr and data

* Chore: force assign name for load/store unit

* RS: add rs'support for store a-d split

* StoreQueue: fix stlf logic

* StoreQueue: fix addr wb sq update logic

* AtomicsUnit: support splited a/d

* Parameters: disable store set by default

* WaitTable: wait table will not cause store delay

* WaitTable: recover default reset period to 2^17

* Fix dev-stad merge conflict

* StoreSet: enable storeset

* RS: disable store rs delay logic

CI perf shows that current delay logic will cause perf loss. Disable
unnecessary delay logic will help.

To be more specific, `io.readyVec` caused the problem. It will be
updated in future commits.

* RS: opt select logic with load delay (ldWait)

* StoreSet: disable 2-bit lwt
Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn>

MinimalConfig limited queues' size, disabled TAGE to limit generated
verilog size

Usage: change `config = DefaultConfig` to `config = MinimalConfig`
in Top.scala / SimTop.scala

In this commit, we add support for using DPI-C calls to replace
DCache, PTW and L1plusCache. L2Cache and L3 Cache are also allowed to
be ignored or bypassed. Configurations are controlled by useFakeDCache,
useFakePTW, useFakeL1plusCache, useFakeL2Cache and useFakeL3Cache.
However, some configurations may not work correctly.

* difftest: use DPI-C to refactor difftest

In this commit, difftest is refactored with DPI-C calls.
There're a few reasons:
(1) From Verilator's manual, DPI-C calls should be more efficient than accessing from dut_ptr.
(2) DPI-C is cross-platform (Verilator, VCS, ...)
(3) difftest APIs are splited from emu.cpp to possibly support more backend platforms
(NEMU, Spike, ...)

The performance at this commit is quite slower than the original emu.
Performance issues will be fixed later.

* [WIP] SimTop: try to use 'XSTop' as soc

* CircularQueuePtr: ues F-bounded polymorphis instead implict helper

* Refactor parameters & Clean up code

* difftest: support basic difftest

* Support diffetst in new sim top

* Difftest; convert recode fmt to ieee754 when comparing fp regs

* Difftest: pass sign-ext pc to dpic functions && fix exception pc

* Debug: add int/exc inst wb to debug queue

* Difftest: pass sign-ext pc to dpic functions && fix exception pc

* Difftest: fix naive commit num limit
Co-authored-by: NYinan Xu <xuyinan1997@gmail.com>
Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>