BPU: Fix Bim read idx bug

Fix Bim read idx bug
Remove valids in BranchPredictionResp
Modify out from Decoupled to Output in BasePredictorIO

src/main/scala/xiangshan/Parameters.scala

@@ -82,12 +82,12 @@ case class XSCoreParameters
       // tage.io.resp_in(0)  := btb.io.resp
       // loop.io.resp_in(0)  := tage.io.resp
       ubtb.io.in.bits.resp_in(0)  := resp_in
-      bim.io.in.bits.resp_in(0)   := ubtb.io.out.bits.resp
-      ftb.io.in.bits.resp_in(0)   := bim.io.out.bits.resp
+      bim.io.in.bits.resp_in(0)   := ubtb.io.out.resp
+      ftb.io.in.bits.resp_in(0)   := bim.io.out.resp
       // tage.io.in.bits.resp_in(0)  := ftb.io.out.bits.resp
 
       // (preds, tage.io.out.bits.resp)
-      (preds, ftb.io.out.bits.resp)
+      (preds, ftb.io.out.resp)
     }),
 
 

src/main/scala/xiangshan/decoupled-frontend/BPU.scala

@@ -138,7 +138,8 @@ class BasePredictorOutput (implicit p: Parameters) extends XSBundle with HasBPUC
 
 class BasePredictorIO (implicit p: Parameters) extends XSBundle with HasBPUConst {
   val in  = Flipped(DecoupledIO(new BasePredictorInput)) // TODO: Remove DecoupledIO
-  val out = DecoupledIO(new BasePredictorOutput)
+  // val out = DecoupledIO(new BasePredictorOutput)
+  val out = Output(new BasePredictorOutput)
   val flush_out = Valid(UInt(VAddrBits.W))
 
   val s0_fire = Input(Bool())
@@ -160,9 +161,9 @@ abstract class BasePredictor(implicit p: Parameters) extends XSModule with HasBP
 
   val io = IO(new BasePredictorIO())
 
-  io.out.bits.resp := io.in.bits.resp_in(0)
+  io.out.resp := io.in.bits.resp_in(0)
 
-  io.out.bits.s3_meta := 0.U
+  io.out.s3_meta := 0.U
 
   io.in.ready := !io.redirect.valid
 
@@ -175,7 +176,7 @@ abstract class BasePredictor(implicit p: Parameters) extends XSModule with HasBP
   val s2_pc       = RegEnable(s1_pc, io.s1_fire)
   val s3_pc       = RegEnable(s2_pc, io.s2_fire)
 
-  io.out.valid := io.in.valid && !io.redirect.valid
+  // io.out.valid := io.in.valid && !io.redirect.valid
 
   // val s0_mask = io.f0_mask
   // val s1_mask = RegNext(s0_mask)
@@ -207,9 +208,8 @@ abstract class BasePredictor(implicit p: Parameters) extends XSModule with HasBP
 
 class FakePredictor(implicit p: Parameters) extends BasePredictor {
   io.in.ready                 := true.B
-  io.out.valid                := io.in.fire
-  io.out.bits.s3_meta         := 0.U
-  io.out.bits.resp := io.in.bits.resp_in(0)
+  io.out.s3_meta         := 0.U
+  io.out.resp := io.in.bits.resp_in(0)
 }
 
 class BpuToFtqIO(implicit p: Parameters) extends XSBundle {
@@ -279,9 +279,9 @@ class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst {
   val s1_ready, s2_ready, s3_ready = Wire(Bool())
   val s1_components_ready, s2_components_ready, s3_components_ready = Wire(Bool())
 
-  val s1_bp_resp = predictors.io.out.bits.resp.s1
-  val s2_bp_resp = predictors.io.out.bits.resp.s2
-  val s3_bp_resp = predictors.io.out.bits.resp.s3
+  val s1_bp_resp = predictors.io.out.resp.s1
+  val s2_bp_resp = predictors.io.out.resp.s2
+  val s3_bp_resp = predictors.io.out.resp.s3
 
   predictors.io := DontCare
   predictors.io.in.valid := s0_fire
@@ -291,7 +291,7 @@ class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst {
   // predictors.io.in.bits.resp_in(0).s1.pc := s0_pc
   predictors.io.in.bits.toFtq_fire := toFtq_fire
 
-  predictors.io.out.ready := io.bpu_to_ftq.resp.ready
+  // predictors.io.out.ready := io.bpu_to_ftq.resp.ready
 
   // Pipeline logic
   s2_redirect := false.B
@@ -336,9 +336,10 @@ class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst {
 
 
   // predictor override redirect
-  val resp_valid = predictors.io.out.bits.resp.valids
-  val finalPredValid = resp_valid(2)
-  val finalPredResp = predictors.io.out.bits.resp
+  // val resp_valid = predictors.io.out.resp.valids
+  // val finalPredValid = resp_valid(2)
+  val finalPredValid = s2_fire
+  val finalPredResp = predictors.io.out.resp
   when(finalPredValid) {
     when(finalPredResp.s2.preds.target =/= RegNext(s0_pc)) {
       s2_redirect := true.B
@@ -355,15 +356,15 @@ class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst {
   // io.bpu_to_ftq.resp.bits.preds := predictors.io.out.bits.resp.s3.preds
   // io.bpu_to_ftq.resp.bits.meta  := predictors.io.out.bits.resp.s3.meta
   io.bpu_to_ftq.resp.valid := s3_fire && !io.ftq_to_bpu.redirect.valid
-  io.bpu_to_ftq.resp.bits  := predictors.io.out.bits.resp.s3
+  io.bpu_to_ftq.resp.bits  := predictors.io.out.resp.s3
 
-  val resp = predictors.io.out.bits.resp
+  val resp = predictors.io.out.resp
 
   when(io.ftq_to_bpu.redirect.valid) {
     s0_pc := io.ftq_to_bpu.redirect.bits.cfiUpdate.target
   }.elsewhen(s2_redirect) {
     s0_pc := finalPredResp.s2.preds.target
-  }.elsewhen(resp.valids(0)) {
+  }.elsewhen(s1_fire) {
     s0_pc := resp.s1.preds.target
   }.otherwise {
     s0_pc := s0_pc_reg

src/main/scala/xiangshan/decoupled-frontend/Bim.scala

@@ -37,20 +37,20 @@ class BIM(implicit p: Parameters) extends BasePredictor with BimParams with BPUU
   resetRow := resetRow + doing_reset
   when (resetRow === (bimSize-1).U) { doing_reset := false.B }
 
-  val s1_idx = bimAddr.getIdx(s1_pc)
+  val s0_idx = bimAddr.getIdx(s0_pc)
 
   bim.io.r.req.valid := io.s0_fire
-  bim.io.r.req.bits.setIdx := s1_idx
+  bim.io.r.req.bits.setIdx := s0_idx
 
-  io.in.ready := bim.io.r.req.ready && !io.redirect.valid
-  io.s1_ready := bim.io.r.req.ready && !io.redirect.valid
-  io.out.valid := io.s2_fire && !io.redirect.valid
+  io.in.ready := bim.io.r.req.ready
+  io.s1_ready := bim.io.r.req.ready
+  // io.out.valid := io.s2_fire && !io.redirect.valid
 
   // val s1_pc = RegEnable(s0_pc, s0_valid)
 
   val s1_read = bim.io.r.resp.data
 
-  io.out.bits.resp := io.in.bits.resp_in(0)
+  io.out.resp := io.in.bits.resp_in(0)
   // io.out.bits.resp.s1.preds.taken_mask := Cat(0.U(1.W), s1_read(1)(1), s1_read(0)(1))
   // io.out.bits.resp.s1.preds.taken_mask := VecInit(Cat(0.U(1.W), s1_read(0)(1)).asBools())
   // io.out.bits.resp.s1.meta := s1_read.asUInt()
@@ -58,10 +58,10 @@ class BIM(implicit p: Parameters) extends BasePredictor with BimParams with BPUU
   val s1_latch_taken_mask = VecInit(Cat(0.U(1.W), Cat((0 until numBr reverse).map(i => s1_read(i)(1)))).asBools())
   val s1_latch_meta       = s1_read.asUInt()
 
-  io.out.bits.resp.s2.preds.taken_mask := RegEnable(s1_latch_taken_mask, 0.U.asTypeOf(Vec(numBr+1, Bool())), io.s1_fire)
+  io.out.resp.s2.preds.taken_mask := RegEnable(s1_latch_taken_mask, 0.U.asTypeOf(Vec(numBr+1, Bool())), io.s1_fire)
 
-  io.out.bits.resp.s3.preds.taken_mask := RegEnable(RegEnable(s1_latch_taken_mask, io.s1_fire), io.s2_fire)
-  io.out.bits.s3_meta := RegEnable(RegEnable(s1_latch_meta, io.s1_fire), io.s2_fire)
+  io.out.resp.s3.preds.taken_mask := RegEnable(RegEnable(s1_latch_taken_mask, io.s1_fire), io.s2_fire)
+  io.out.s3_meta := RegEnable(RegEnable(s1_latch_meta, io.s1_fire), io.s2_fire)
 
   // Update logic
   val u_valid = RegNext(io.update.valid)

src/main/scala/xiangshan/decoupled-frontend/Composer.scala

@@ -23,7 +23,7 @@ import utils._
 
 class Composer(implicit p: Parameters) extends BasePredictor with HasBPUConst {
   val (components, resp) = getBPDComponents(io.in.bits.resp_in(0), p)
-  io.out.bits.resp := resp
+  io.out.resp := resp
 
   var metas = 0.U(1.W)
   var meta_sz = 0
@@ -33,7 +33,7 @@ class Composer(implicit p: Parameters) extends BasePredictor with HasBPUConst {
     c.io.in.bits.ghist      := io.in.bits.ghist
     c.io.in.bits.toFtq_fire := io.in.bits.toFtq_fire
     if (c.meta_size > 0) {
-      metas = (metas << c.meta_size) | c.io.out.bits.s3_meta(c.meta_size-1,0)
+      metas = (metas << c.meta_size) | c.io.out.s3_meta(c.meta_size-1,0)
     }
     meta_sz = meta_sz + c.meta_size
   }
@@ -49,7 +49,7 @@ class Composer(implicit p: Parameters) extends BasePredictor with HasBPUConst {
   components.foreach(_.io.s2_fire := io.s2_fire)
   components.foreach(_.io.s3_fire := io.s3_fire)
 
-  io.out.bits.resp.valids := VecInit(components.map(_.io.out.valid))
+  // io.out.bits.resp.valids := VecInit(components.map(_.io.out.valid))
 
   when(io.redirect.valid) {
     s0_pc := io.redirect.bits.cfiUpdate.target
@@ -57,7 +57,7 @@ class Composer(implicit p: Parameters) extends BasePredictor with HasBPUConst {
 
 
   require(meta_sz < MaxMetaLength)
-  io.out.bits.s3_meta := metas
+  io.out.s3_meta := metas
 
 
   var update_meta = io.update.bits.meta

src/main/scala/xiangshan/decoupled-frontend/FTB.scala

@@ -100,9 +100,9 @@ class FTB(implicit p: Parameters) extends BasePredictor with FTBParams {
   io.in.ready := ftb.io.r.req.ready && !io.redirect.valid // TODO: remove
   io.s1_ready := ftb.io.r.req.ready && !io.redirect.valid
   // io.out.valid := RegEnable(RegNext(io.s0_fire), io.s1_fire) && !io.flush.valid
-  io.out.valid := io.s2_fire && !io.redirect.valid
+  // io.out.valid := io.s2_fire && !io.redirect.valid
 
-  io.out.bits.resp.valids(1) := io.out.valid
+  // io.out.bits.resp.valids(1) := io.out.valid
 
   val s1_read = VecInit((0 until numWays).map(w =>
     ftb.io.r.resp.data(w)
@@ -144,7 +144,7 @@ class FTB(implicit p: Parameters) extends BasePredictor with FTBParams {
   val jmpTarget = ftb_entry.jmpTarget
 
   // io.out.bits.resp := RegEnable(io.in.bits.resp_in(0), 0.U.asTypeOf(new BranchPredictionResp), io.s1_fire)
-  io.out.bits.resp := io.in.bits.resp_in(0)
+  io.out.resp := io.in.bits.resp_in(0)
 
   val s1_latch_target = Wire(UInt(VAddrBits.W))
   // s1_latch_target := io.in.bits.resp_in(0).s1.preds.target
@@ -167,26 +167,26 @@ class FTB(implicit p: Parameters) extends BasePredictor with FTBParams {
 
   val s1_latch_call_is_rvc   = DontCare // TODO: modify when add RAS
 
-  io.out.bits.resp.s2.preds.taken_mask    := RegEnable(s1_latch_taken_mask, io.s1_fire)
-  io.out.bits.resp.s2.preds.is_br         := RegEnable(ftb_entry.brValids, io.s1_fire)
-  io.out.bits.resp.s2.preds.is_jal        := RegEnable(ftb_entry.jmpValid && !ftb_entry.isJalr, io.s1_fire)
-  io.out.bits.resp.s2.preds.is_jalr       := RegEnable(ftb_entry.isJalr, io.s1_fire)
-  io.out.bits.resp.s2.preds.is_call       := RegEnable(ftb_entry.isCall, io.s1_fire)
-  io.out.bits.resp.s2.preds.is_ret        := RegEnable(ftb_entry.isRet, io.s1_fire)
+  io.out.resp.s2.preds.taken_mask    := RegEnable(s1_latch_taken_mask, io.s1_fire)
+  io.out.resp.s2.preds.is_br         := RegEnable(ftb_entry.brValids, io.s1_fire)
+  io.out.resp.s2.preds.is_jal        := RegEnable(ftb_entry.jmpValid && !ftb_entry.isJalr, io.s1_fire)
+  io.out.resp.s2.preds.is_jalr       := RegEnable(ftb_entry.isJalr, io.s1_fire)
+  io.out.resp.s2.preds.is_call       := RegEnable(ftb_entry.isCall, io.s1_fire)
+  io.out.resp.s2.preds.is_ret        := RegEnable(ftb_entry.isRet, io.s1_fire)
 
-  io.out.bits.resp.s2.preds.target        := RegEnable(s1_latch_target, io.s1_fire)
-  io.out.bits.resp.s2.pc                  := RegEnable(s1_pc, io.s1_fire) //s2_pc
-  io.out.bits.resp.s2.hit                 := RegEnable(s1_hit, io.s1_fire)
-  io.out.bits.resp.s2.ftb_entry           := RegEnable(ftb_entry, io.s1_fire)
+  io.out.resp.s2.preds.target        := RegEnable(s1_latch_target, io.s1_fire)
+  io.out.resp.s2.pc                  := RegEnable(s1_pc, io.s1_fire) //s2_pc
+  io.out.resp.s2.hit                 := RegEnable(s1_hit, io.s1_fire)
+  io.out.resp.s2.ftb_entry           := RegEnable(ftb_entry, io.s1_fire)
 
-  io.out.bits.s3_meta                     := RegEnable(RegEnable(FTBMeta(writeWay.asUInt(), s1_hit).asUInt(), io.s1_fire), io.s2_fire)
+  io.out.s3_meta                     := RegEnable(RegEnable(FTBMeta(writeWay.asUInt(), s1_hit).asUInt(), io.s1_fire), io.s2_fire)
 
-  io.out.bits.resp.s3 := RegEnable(io.out.bits.resp.s2, io.s2_fire)
+  io.out.resp.s3 := RegEnable(io.out.resp.s2, io.s2_fire)
 
   when(!s2_hit) {
-    io.out.bits.resp.s2.ftb_entry.pftAddr := RegEnable(s1_pc + (FetchWidth*4).U, io.s1_fire)
+    io.out.resp.s2.ftb_entry.pftAddr := RegEnable(s1_pc + (FetchWidth*4).U, io.s1_fire)
   }.otherwise {
-    io.out.bits.resp.s2.ftb_entry.pftAddr := RegEnable(ftb_entry.pftAddr, io.s1_fire)
+    io.out.resp.s2.ftb_entry.pftAddr := RegEnable(ftb_entry.pftAddr, io.s1_fire)
   }
 
   // Update logic

src/main/scala/xiangshan/decoupled-frontend/FrontendBundle.scala

@@ -118,7 +118,7 @@ class BranchPredictionBundle(implicit p: Parameters) extends XSBundle with HasBP
 }
 
 class BranchPredictionResp(implicit p: Parameters) extends XSBundle with HasBPUConst {
-  val valids = Vec(3, Bool())
+  // val valids = Vec(3, Bool())
   val s1 = new BranchPredictionBundle()
   val s2 = new BranchPredictionBundle()
   val s3 = new BranchPredictionBundle()

src/main/scala/xiangshan/decoupled-frontend/RAS.scala

@@ -159,9 +159,9 @@ class RAS(implicit p: Parameters) extends BasePredictor {
   spec_ras.recover_top := recover_cfi.rasEntry
   spec_ras.recover_new_addr := recover_cfi.pc + Mux(recover_cfi.pd.isRVC, 2.U, 4.U)
 
-  io.out.bits.s3_meta := Cat(spec_ras.sp, spec_ras.top.asUInt())
+  io.out.s3_meta := Cat(spec_ras.sp, spec_ras.top.asUInt())
 
-  io.out.bits.resp.s3.preds.target := spec_top_addr
+  io.out.resp.s3.preds.target := spec_top_addr
   // TODO: back-up stack for ras
   // use checkpoint to recover RAS
 }

src/main/scala/xiangshan/decoupled-frontend/Tage.scala

@@ -495,7 +495,7 @@ class Tage(implicit p: Parameters) extends BaseTage {
     if3_providerUs(w) := if3_resps(if3_provider)(w).bits.u
     if3_providerCtrs(w) := if3_resps(if3_provider)(w).bits.ctr
 
-    val resp = io.out.bits.resp.s3
+    val resp = io.out.resp.s3
 
     resp.preds.taken_mask(w) := if4_tageTakens(w) // && ctrl.tage_enable
 

src/main/scala/xiangshan/decoupled-frontend/uBTB.scala

@@ -215,22 +215,22 @@ class MicroBTB(implicit p: Parameters) extends BasePredictor
   banks.read_pc.valid := io.s1_fire
   banks.read_pc.bits := s1_pc
 
-  io.out.valid := io.s1_fire && !io.redirect.valid
-  io.out.bits.resp := io.in.bits.resp_in(0)
-  io.out.bits.resp.valids(0) := io.out.valid
-  io.out.bits.resp.s1.pc := s1_pc
+  // io.out.valid := io.s1_fire && !io.redirect.valid
+  io.out.resp := io.in.bits.resp_in(0)
+  // io.out.resp.valids(0) := io.out.valid
+  io.out.resp.s1.pc := s1_pc
   // io.out.bits.resp.s1.meta := read_resps.pred.asUInt() // TODO: What ubtb meta need
-  io.out.bits.s3_meta := RegEnable(RegEnable(read_resps.pred.asUInt(), io.s1_fire), io.s2_fire) // s3_meta
+  io.out.s3_meta := RegEnable(RegEnable(read_resps.pred.asUInt(), io.s1_fire), io.s2_fire) // s3_meta
   // io.out.bits.resp.s1.preds.target := Mux(banks.read_hit, read_resps.target, s1_pc + (FetchWidth*4).U)
-  io.out.bits.resp.s1.preds.target := Mux(banks.read_hit, read_resps.target, s1_pc + (FetchWidth*4).U)
-  io.out.bits.resp.s1.preds.taken_mask := read_resps.taken_mask
+  io.out.resp.s1.preds.target := Mux(banks.read_hit, read_resps.target, s1_pc + (FetchWidth*4).U)
+  io.out.resp.s1.preds.taken_mask := read_resps.taken_mask
   // io.out.bits.resp.s1.preds.is_br := read_resps.brValids
   // io.out.bits.resp.s1.preds.is_jal := read_resps.jmpValid && !(read_resps.isCall || read_resps.isRet || read_resps.isJalr)
   // io.out.bits.resp.s1.preds.is_jalr := read_resps.jmpValid && read_resps.isJalr
   // io.out.bits.resp.s1.preds.is_call := read_resps.jmpValid && read_resps.isCall
   // io.out.bits.resp.s1.preds.is_ret := read_resps.jmpValid && read_resps.isRet
   // io.out.bits.resp.s1.preds.call_is_rvc := read_resps.last_is_rvc
-  io.out.bits.resp.s1.hit := banks.read_hit
+  io.out.resp.s1.hit := banks.read_hit
 
   // Update logic
   val update = RegNext(io.update.bits)