* previously we only modify jmpTarget on misprediction, and that's
  because we only use ftb to predict jalr target. However, with the
  presence of an indirect branch predictor, there exists such case
  that an indirect branch is correctly predicted when the target in
  ftb entry is wrong.

config: remove MinimalSimConfigForFetch

bundle: code clean ups

bundle, xscore: code clean ups

* IntToFP: support fully pipelined mode

This commit adds fastUopOut support for pipelined function units via
implementing fastUopOut in trait HasPipelineReg.

The following function units now support fastUopOut:
- MUL
- FMA
- F2I
- F2F

* Add submodule 'fudian'

* IntToFP: use fudian

* FMA: use fudian.CMA

* FPToInt: remove recode format

* Alu: optimize timing

This pull request optimizes timing by adding a 32bit adder for addw and changing the encode.

This commit optimizes ExuBlock timing by connecting writeback when
possible.

The timing priorities are RegNext(rs.fastUopOut) > fu.writeback >
arbiter.out(--> io.rfWriteback --> rs.writeback). The higher priority,
the better timing.

(1) When function units have exclusive writeback ports, their
wakeup ports for reservation stations can be connected directly from
function units' writeback ports. Special case: when the function unit
has fastUopOut, valid and uop should be RegNext.

(2) If the reservation station has fastUopOut for all instructions
in this exu, we should replace io.fuWriteback with RegNext(fastUopOut).
In this case, the corresponding execution units must have exclusive
writeback ports, unless it's impossible that rs can ensure the
instruction is able to write the regfile.

(3) If the reservation station has fastUopOut for all instructions in
this exu, we should replace io.rfWriteback (rs.writeback) with
RegNext(rs.wakeupOut).

* bump chisel to 3.5

* Remove deprecated 'toBool' && disable tl monitor

* Update RocketChip / Re-enable TLMonitor

* Makefile: remove '--infer-rw'

* mmu: wrap l2tlb's param withL2TLBParameters

* mmu.l2tlb: add param blockBytes: 64, 8 ptes

* mmu.l2tlb: set l2tlb cache size to l2:256, l3:4096

* mmu.l2tlb: add config print

* mmu.l2tlb: fix bug of resp data indices choosen and opt coding style

* rs,bypass: remove optBuf for valid bits

* rs,bypass: add left and right bypass strategy

This commit adds another bypass network implementation to optimize timing of the first stage of function units.

In BypassNetworkLeft, we bypass data at the same cycle that function units write data back. This increases the length of the critical path of the last stage of function units but reduces the length of the critical path of the first stage of function units. Some function units that require a shorter stage zero, like LOAD, may use BypassNetworkLeft.

In this commit, we set all bypass networks to the left style, but we will make it configurable depending on different function units in the future.

This commit changes how io.out is computed for age detector. We use a
register to keep track of the position of the oldest instruction. Since
the updating information has better timing than issue, this could
optimize the timing of issue logic.

* modify UBitPeriod to one-eights of the previous value to adapt
  to nRows enlarged by eight times
* fix a bug assigning sc update mask

bpu: add redirect logic between stages for circumstances where directions differ but targets remain the same

This commit reduces register usage in age detector via using the
upper matrix only. Since the age matrix is symmetric, age(i)(j)
equals !age(j)(i). Besides, age(i)(i) is the same as valid(i).
Thus, we also remove validVec in this commit.

This commit adds a fastUopOut option to function units. This allows the
function units to give valid and uop one cycle before its output data is
ready. FastUopOut lets writeback arbitration happen one cycle before
data is ready and helps optimize the timing.

Since some function units are not ready for this new feature, this
commit adds a fastImplemented option to allow function units to have
fastUopOut but the data is still at the same cycle as uop. This option
will delay the data for one cycle and may cause performance degradation.
FastImplemented should be true after function units support fastUopOut.

* This will be a problem when a RVI jal is the last instrution of a basic
block. The realEndPC will greater than startAddr + 32 bytes.

This commit adds support for directly connecting data from function
units if the function units exclusively own the writeback ports. This
happens for ALU and FMA currently.

* write ubtb meta and data at the same time
* fix fallThruError method

* separate the Alu instructions by 64bit data instructions and w-suffix instructions
* optimize select logic of instructions result

* fix a bug when establishing new ftb entry with a jalr
* use ftb hit signal instead of ubtb to assign entry_hit_status
* move always taken logic to ftb

* Refactor print control transform

* Adda tilelink bus pmu

* Add performance counters for dispatch, issue, execute stages

* Add more counters in bus pmu

* Insert BusPMU between L3 and L2

* add some TMA perfcnt
Co-authored-by: NLinJiawei <linjiawei20s@ict.ac.cn>
Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>
Co-authored-by: Nwangkaifan <wangkaifan@ict.ac.cn>