But this would not work(for syntax bug) until other modules change

1. divide into three block
2. change io port:
  broadcastUop -> fastUopsIn
  selectUop    -> fastUopOut
  extraPorts   -> slowPorts
  etc.
the cross sub block io is not wrapped, to it later

ReservationStation: change width of srcRegValue into (XLEN+1)

from 8/12 to 4

Note: running microbench with seed 4956 will fail on a tilelink assert