Dispatch/Block: update regRdy + readPorts choosing logic

src/main/scala/xiangshan/backend/FloatBlock.scala

@@ -90,10 +90,13 @@ class FloatBlock
     rsCtrl.io.enqCtrl <> io.fromCtrlBlock.enqIqCtrl(i)
 
     rsData.io.srcRegValue := DontCare
-    val srcIndex = List.tabulate(3)(Range(_, 12, 3).map(_.U))
-    rsData.io.srcRegValue(0) := fpRf.io.readPorts(LookupTree(readPortIndex(i), (0 until 4).map(_.U).zip(srcIndex(0)))).data
-    rsData.io.srcRegValue(1) := fpRf.io.readPorts(LookupTree(readPortIndex(i), (0 until 4).map(_.U).zip(srcIndex(1)))).data
-    rsData.io.srcRegValue(2) := fpRf.io.readPorts(LookupTree(readPortIndex(i), (0 until 4).map(_.U).zip(srcIndex(2)))).data
+    val src1Value = VecInit((0 until 4).map(i => fpRf.io.readPorts(i * 3).data))
+    val src2Value = VecInit((0 until 4).map(i => fpRf.io.readPorts(i * 3 + 1).data))
+    val src3Value = VecInit((0 until 4).map(i => fpRf.io.readPorts(i * 3 + 2).data))
+    
+    rsData.io.srcRegValue(0) := src1Value(readPortIndex(i))
+    rsData.io.srcRegValue(1) := src2Value(readPortIndex(i))
+    rsData.io.srcRegValue(2) := src3Value(readPortIndex(i))
     rsData.io.redirect <> redirect
 
     rsData.io.writeBackedData <> writeBackData

src/main/scala/xiangshan/backend/IntegerBlock.scala

@@ -144,8 +144,10 @@ class IntegerBlock
     rsCtrl.io.enqCtrl <> io.fromCtrlBlock.enqIqCtrl(i)
 
     rsData.io.srcRegValue := DontCare
-    rsData.io.srcRegValue(0) := intRf.io.readPorts(Cat(readPortIndex(i), 0.U(1.W))).data // readPortIndex(i) * 2.U
-    rsData.io.srcRegValue(1) := intRf.io.readPorts(Cat(readPortIndex(i), 1.U(1.W))).data // readPortIndex(i) * 2.U + 1.U
+    val src1Value = VecInit((0 until 4).map(i => intRf.io.readPorts(i * 2).data))
+    val src2Value = VecInit((0 until 4).map(i => intRf.io.readPorts(i * 2 + 1).data))
+    rsData.io.srcRegValue(0) := src1Value(readPortIndex(i))
+    rsData.io.srcRegValue(1) := src2Value(readPortIndex(i))
     rsData.io.redirect <> redirect
 
     rsData.io.writeBackedData <> writeBackData

src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala

@@ -87,12 +87,14 @@ class Dispatch2Fp extends XSModule {
     val enq = io.enqIQCtrl(i)
     enq.valid := validVec(i)
     enq.bits := io.fromDq(indexVec(i)).bits
-    val srcIndex = List.tabulate(3)(Range(_, 12, 3).map(_.U)).map(table => LookupTree(readPortIndex(i), (0 until 4).map(_.U).zip(table)))
-    enq.bits.src1State := io.regRdy(srcIndex(0))
-    enq.bits.src2State := io.regRdy(srcIndex(1))
-    enq.bits.src3State := io.regRdy(srcIndex(2))
+    
+    val src1Ready = VecInit((0 until 4).map(i => io.regRdy(i * 3)))
+    val src2Ready = VecInit((0 until 4).map(i => io.regRdy(i * 3 + 1)))
+    val src3Ready = VecInit((0 until 4).map(i => io.regRdy(i * 3 + 2)))
+    enq.bits.src1State := src1Ready(readPortIndex(i))
+    enq.bits.src2State := src2Ready(readPortIndex(i))
+    enq.bits.src3State := src3Ready(readPortIndex(i))
 
-    XSInfo(enq.fire(), p"srcIndices: ${srcIndex(0)} ${srcIndex(1)} ${srcIndex(2)}, readPortIndex: ${readPortIndex(i)}\n")
     XSInfo(enq.fire(), p"pc 0x${Hexadecimal(enq.bits.cf.pc)} with type ${enq.bits.ctrl.fuType} " +
       p"srcState(${enq.bits.src1State} ${enq.bits.src2State} ${enq.bits.src3State}) " +
       p"enters reservation station $i from ${indexVec(i)}\n")

src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala

@@ -89,8 +89,11 @@ class Dispatch2Int extends XSModule {
     val enq = io.enqIQCtrl(i)
     enq.valid := validVec(i)
     enq.bits := io.fromDq(indexVec(i)).bits
-    enq.bits.src1State := io.regRdy(Cat(readPortIndex(i), 0.U(1.W)))
-    enq.bits.src2State := io.regRdy(Cat(readPortIndex(i), 1.U(1.W)))
+    
+    val src1Ready = VecInit((0 until 4).map(i => io.regRdy(i * 2)))
+    val src2Ready = VecInit((0 until 4).map(i => io.regRdy(i * 2 + 1)))
+    enq.bits.src1State := src1Ready(readPortIndex(i))
+    enq.bits.src2State := src2Ready(readPortIndex(i))
 
     XSInfo(enq.fire(), p"pc 0x${Hexadecimal(enq.bits.cf.pc)} with type ${enq.bits.ctrl.fuType} " +
       p"srcState(${enq.bits.src1State} ${enq.bits.src2State}) " +