- 07 7月, 2022 1 次提交
-
-
由 Yinan Xu 提交于
This commit fixes the bug that the lsrc(0) of trap instructions is overrided with $a0, which causes timing issues as well.
-
- 06 7月, 2022 12 次提交
-
-
由 Yinan Xu 提交于
This commit adds a pipeline for performance counters. No functional changes.
-
由 huxuan0307 提交于
* Remove unused field isRVF * Replace 3rd srcType of non-fp insts and FuType.{fmisc, i2f} insts with SrcType.X
-
由 Yinan Xu 提交于
Some modules rely on the walk valid bits of ROB. This commit optimizes the timing by providing separated walk valid bits, which is far better than the commit valid bits.
-
由 Yinan Xu 提交于
This commit changes the data modules in Dispatch Queue. We use one-hot indices to read and write the data array.
-
由 Yinan Xu 提交于
Optimize the naive implementation of performance counters in decode.
-
由 William Wang 提交于
-
由 William Wang 提交于
-
由 William Wang 提交于
Now bank conflict replay hint will be send to rs in load_s2 Will cause perf loss
-
由 William Wang 提交于
-
由 William Wang 提交于
-
由 William Wang 提交于
It will add l1 dcache miss latency by 1 cycle
-
由 William Wang 提交于
Instructions with page fault or access fault will flush later instructions, hence it is safe to ignore access fault and page fault when generate fastUop.valid Now fastUop.valid do not care about perm read from dtlb sram
-
- 30 6月, 2022 1 次提交
-
-
由 Lingrui98 提交于
* add one cycle stall to ftb miss update, and * add one cycle delay to all other predictors
-
- 29 6月, 2022 2 次提交
- 28 6月, 2022 1 次提交
-
-
由 William Wang 提交于
This commit re-pipelines ECC check logic in data cache and exception generate logic for better timing. Now ecc error is checked 1 cycle after reading result from data sram. An extra cycle is added for load writeback to ROB. Future work: move the pipeline to https://github.com/OpenXiangShan/XiangShan/blob/master/src/main/scala/xiangshan/backend/CtrlBlock.scala#L266-L277, which add a regnext. * dcache: repipeline ecc check logic for timing * chore: fix normal loadAccessFault logic * wbu: delay load unit wb for 1 cycle * dcache: add 1 extra cycle for beu error report
-
- 27 6月, 2022 3 次提交
-
-
由 Yinan Xu 提交于
* dp2: add a pipeline for load/store Load/store Dispatch2 has a bad timing because it requires the fuType to disguish the out ports. This brings timing issues because the instruction has to read busyTable after the port arbitration. This commit adds a pipeline in dp2Ls, which may cause performance degradation. Instructions are dispatched according to out, and at the next cycle it will leave dp2. * bump difftest trying to fix vcs
-
由 William Wang 提交于
* dcache: do not access plru when refill Now we have accessed plru when load miss, we should not access plru when refill * dcache: not not access plru when miss queue full It will help avoid invalid plru access when miss queue full
-
由 zhanglinjuan 提交于
-
- 26 6月, 2022 1 次提交
-
-
由 Lemover 提交于
fix some bugs. 1. fix l2tlb dead-lock bug l2tlb won't merge requests at same addr. It will be blocked when having too many requests. PtwFilter has a bug that will send too many requests. Add a counter to avoid that. 2. fix sfence sync at mmu different modules in mmu may get sfence at different latency, which will lost requests or some requests have no receiver. Sync the sfence latency manually to avoid the bug. * mmu.filter: add counter not to send to many req to l2tlb * mmu.filter: fix bug that forget counter signal when block issue and deq * mmu: set sfence/csr delay to 2 cycle, must sync in mmu
-
- 25 6月, 2022 3 次提交
-
-
由 Lemover 提交于
now the l2tlb page cache are divided into: 1. stageReq: input && read sram valid && will block when sram write 2. stageDelay: get sram data and delay one cycle 3. stageCheck: check hit and ecc result 4. stageResp: output
-
由 Lemover 提交于
Background: dtlb has 128 entries stored in sram. 128 sets, 1 ways. advantage: large volume & 1 ways means no tag match logic at data select path disadvantage: 128 sets means long latency at valid select, which is a Vec-Register. Optimization: divide valid select into two-cycles
-
由 Yinan Xu 提交于
This commit optimizes the timing of freelist by changing the updating function of headPtr and tailPtr. We maintains an one-hot representation of headPtr and further uses it to read the free registers from the list, which should be better than the previous implementation where headPtr is used to indexed into the queue. The update of tailPtr and the freelist is delayed by one cycle to optimize the timing. Because freelist allocates new registers in the next cycle iff there are more than RenameWidth free registers in this cycle. The freed registers in this cycle will never be used in the next cycle. Thus, we can delay the updating of queue data to the next cycle. We also move the update of tailPtr to the next cycle, since PopCount takes a long timing and we move the last adder to the next cycle. Now the adder works parallely with PopCount. That is, the updating of tailPtr is pipelined.
-
- 24 6月, 2022 1 次提交
-
-
由 LinJiawei 提交于
-
- 22 6月, 2022 1 次提交
-
-
由 Yinan Xu 提交于
This commit adds a buffer after the function unit that operate across the integer block and the floating-point block, such as f2i and i2f. For example, previously the out.ready of f2i depends on whether mul/div/csr/jump has a valid instruction out, since f2i has lower priority than them. This ready back-propagates from the integer function units to the floating-point function units, and finally to the floating-point reservation stations (since f2i is fully pipelined). We add a buffer after the function unit to break this ready back-propagation. It incurs one more cycle of execution latency, but we leave it not-fully-optimized for now. Timing can be further optimized if we separates the int writeback and fp writeback in function units. In the current version, the ready of f2i affects the ready of f2f pipelines, which is unnecessary. This is the future work.
-
- 21 6月, 2022 1 次提交
-
-
由 Yinan Xu 提交于
This commit adds some registers for performance counters to optimize the timing. Pipelines are added.
-
- 20 6月, 2022 2 次提交
-
-
由 Yinan Xu 提交于
-
由 William Wang 提交于
-
- 18 6月, 2022 2 次提交
-
-
由 Yinan Xu 提交于
This commit changes the lsrc/psrc of LUI in dispatch instead of decode to optimize the timing of lsrc in DecodeStage, which is critical for rename table. lsrc/ldest should be directly get from instr for the timing. Fused instructions change lsrc/ldest now, which will be optimized later.
-
由 wakafa 提交于
* buspmu: avoid inner space in perf-cnt name * perfcnt: judge regularity of perfname * perfcnt: fix some irregular perfname * bump huancun
-
- 17 6月, 2022 1 次提交
-
-
由 Ziyue-Zhang 提交于
-
- 11 6月, 2022 1 次提交
-
-
由 Guokai Chen 提交于
-
- 09 6月, 2022 1 次提交
-
-
由 Steve Gou 提交于
last_may_be_rvi_call in case that a call comes after a taken branch
-
- 08 6月, 2022 1 次提交
-
-
由 Lingrui98 提交于
-
- 06 6月, 2022 4 次提交
-
-
由 Jenius 提交于
-
由 Jenius 提交于
* add SRAM ready (resetfinish) condition for *Array (metaArray/dataArray) req.ready
-
由 Jenius 提交于
* fix mmio_resend_af wrong assignment * fix wb_half_flush missOffset(using wb_lastIdx instead of PredictWidth -1) * change pipeline ready condition (this_ready = this_stage_fire || this_stage_empty) * delete 500-cycle ready condition (toICache(*).ready means the SRAM has been reset and ready for read)
-
由 Lemover 提交于
* bump huancun, update Chisel3, revert sram hazard enhancement * util.sram: rm a r/w hazard mux which is not needed. bump huancun
-
- 02 6月, 2022 1 次提交
-
-
由 Lingrui98 提交于
Previous logic checked the value of old_ctr to select between old target and new target when updating ittage table. However, when we need to alloc a new entry, the value of old_ctr is X because we do not reset ittage table. So we would definitely write an X to the target field, which is the output of the mux, as the selector is X.
-