* also put mainargs at 0x80001000 to match AM

* SimpleBusUL is used for MMIO and SimpleBusUH is used for memory
* should refactor SimpleBus2AXI4Converter to support SimpleBusUL and
  SimpleBusUH

* chisel 3.2 supports userBits == 0

* When we flush the pipeline, we should also flush the BTB hit state.
  Otherwise, the redirected instruction will be predicted as hit in BTB,
  and it will generate a wrong npc until the BTB hit state is updated.
  The wrong npc will affect the correct control flow by updating pc,
  which will let IFU fetch a wrong instruction.

* Note that at the time of flushing, we also access BTB to predict the
  npc of the redirected target instruction. After the delay update of
  this patch, it will cause a read write conflict for the single-port
  SRAM. Therefore we disable the prediction of the redirected target
  instruction. This will reduce the IPC: 0.544548 -> 0.543382

* Some small functions will return quickly. `ret` is executed without
  the correct return address pushed into RAS.