opt(IFU): optimize path lateJump->npc->BTB

src/main/scala/noop/IDU.scala

@@ -143,6 +143,8 @@ class IDU extends NOOPModule with HasInstrType {
   // val pnpcIsSeqRight = io.in.bits.pnpc === (Cat(io.in.bits.pc(AddrBits-1,2), 0.U(2.W)) + 4.U) // TODO: add a new user bit bpRight to do this 
   // assert(pnpcIsSeq === pnpcIsSeqRight)
   val flushIFU = (state === s_idle || state === s_extra) && rvcSpecial && io.in.valid && !pnpcIsSeq
+  when(flushIFU){printf("flushIFU at pc %x offset %x\n", io.in.bits.pc, pcOffset)}
+  assert(!flushIFU)
   val loadNextInstline = (state === s_idle || state === s_extra) && (rvcSpecial || rvcSpecialJump) && io.in.valid && pnpcIsSeq
   // val loadNextInstline =false.B
   val pcOut = WireInit(0.U(AddrBits.W))

src/main/scala/noop/IFU.scala

@@ -42,9 +42,9 @@ class IFU extends NOOPModule with HasResetVector {
   val lateJumpForceTgt = lateJumpLatch && !bp1.io.flush
 
   // predicted next pc
-  val pnpc = bp1.io.out.target
+  val pnpc = Mux(lateJump, snpc, bp1.io.out.target)
   val pbrIdx = bp1.io.brIdx
-  val npc = Mux(io.redirect.valid, io.redirect.target, Mux(io.redirectRVC.valid, io.redirectRVC.target, Mux(lateJumpLatch, lateJumpTarget, Mux(lateJump, snpc, Mux(bp1.io.out.valid, pnpc, snpc)))))
+  val npc = Mux(io.redirect.valid, io.redirect.target, Mux(lateJumpLatch, lateJumpTarget, Mux(bp1.io.out.valid, pnpc, snpc)))
   val npcIsSeq = Mux(io.redirect.valid || io.redirectRVC.valid, false.B, Mux(lateJumpLatch, false.B, Mux(lateJump, true.B, Mux(bp1.io.out.valid, false.B, true.B))))
   // val npc = Mux(io.redirect.valid, io.redirect.target, Mux(io.redirectRVC.valid, io.redirectRVC.target, snpc))
   val brIdx = Wire(UInt(4.W))