bus,simplebus: refactor bus requests with apply function

src/main/scala/bus/simplebus/SimpleBus.scala

@@ -40,6 +40,15 @@ class SimpleBusReqBundle(val userBits: Int = 0) extends SimpleBusBundle {
     p"wmask = 0x${Hexadecimal(wmask)}, wdata = 0x${Hexadecimal(wdata)}"
   }
 
+  def apply(addr: UInt, cmd: UInt, size: UInt, wdata: UInt, wmask: UInt, user: UInt = 0.U) {
+    this.addr := addr
+    this.cmd := cmd
+    this.size := size
+    this.wdata := wdata
+    this.wmask := wmask
+    this.user.map(_ := user)
+  }
+
   def isRead() = !cmd(0) && !cmd(3)
   def isWrite() = cmd(0)
   def isBurst() = cmd(1)

src/main/scala/noop/Cache.scala

@@ -170,10 +170,6 @@ sealed class CacheStage3(ro: Boolean, name: String, userBits: Int = 0) extends C
     data = Wire(new MetaBundle).apply(tag = meta.tag, valid = true.B, dirty = (!ro).B)
   )
 
-  // if miss, access memory
-  io.mem := DontCare
-  io.mem.req.bits.size := (if (XLEN == 64) "b11".U else "b10".U)
-
   val s_idle :: s_memReadReq :: s_memReadResp :: s_memWriteReq :: s_memWriteResp :: s_wait_resp :: Nil = Enum(6)
   val state = RegInit(s_idle)
   val needFlush = RegInit(false.B)
@@ -198,17 +194,16 @@ sealed class CacheStage3(ro: Boolean, name: String, userBits: Int = 0) extends C
     is (s2_memWriteReq) { when (io.mem.req.fire()) { state2 := s2_idle } }
   }
 
-  io.mem.req.bits.wdata := Mux1H(io.in.bits.waymask, dataWay).data
-  io.mem.req.bits.wmask := Fill(DataBytes, 1.U)
-  io.mem.req.bits.cmd := Mux(state === s_memReadReq, SimpleBusCmd.readBurst,
-    Mux((writeBeatCnt.value === (LineBeats - 1).U), SimpleBusCmd.writeLast, SimpleBusCmd.writeBurst))
-
-  // critical word first
+  // critical word first read
   val raddr = (if (XLEN == 64) Cat(req.addr(AddrBits-1,3), 0.U(3.W))
                           else Cat(req.addr(AddrBits-1,2), 0.U(2.W)))
   // dirty block addr
   val waddr = Cat(meta.tag, addr.index, 0.U(OffsetBits.W))
-  io.mem.req.bits.addr := Mux(state === s_memReadReq, raddr, waddr)
+  val cmd = Mux(state === s_memReadReq, SimpleBusCmd.readBurst,
+    Mux((writeBeatCnt.value === (LineBeats - 1).U), SimpleBusCmd.writeLast, SimpleBusCmd.writeBurst))
+  io.mem.req.bits.apply(addr = Mux(state === s_memReadReq, raddr, waddr),
+    cmd = cmd, size = (if (XLEN == 64) "b11".U else "b10".U),
+    wdata = Mux1H(io.in.bits.waymask, dataWay).data, wmask = Fill(DataBytes, 1.U))
 
   io.mem.resp.ready := true.B
   io.mem.req.valid := (state === s_memReadReq) || ((state === s_memWriteReq) && (state2 === s2_memWriteReq))

src/main/scala/noop/IFU.scala

@@ -40,12 +40,9 @@ class IFU extends NOOPModule with HasResetVector {
   io.flushVec := Mux(io.redirect.valid, "b1111".U, 0.U)
   io.bpFlush := false.B
 
-  io.imem := DontCare
+  io.imem.req.bits.apply(addr = Cat(pc(AddrBits-1,2),0.U(2.W)), //cache will treat it as Cat(pc(63,3),0.U(3.W))
+    size = "b11".U, cmd = SimpleBusCmd.read, wdata = 0.U, wmask = 0.U, user = npc)
   io.imem.req.valid := io.out.ready
-  io.imem.req.bits.addr := Cat(pc(AddrBits-1,2),0.U(2.W))//cache will treat it as Cat(pc(63,3),0.U(3.W)) 
-  io.imem.req.bits.size := "b11".U
-  io.imem.req.bits.cmd := SimpleBusCmd.read
-  io.imem.req.bits.user.map(_ := npc)
   io.imem.resp.ready := io.out.ready || io.flushVec(0)
 
   io.out.bits := DontCare

src/main/scala/noop/fu/LSU.scala

@@ -80,12 +80,10 @@ class LSU extends NOOPModule {
     is (s_partialLoad) { state := s_idle }
   }
 
-  dmem.req.bits.addr := addr
-  dmem.req.bits.size := func(1, 0)
+  val size = func(1,0)
+  dmem.req.bits.apply(addr = addr, size = size, wdata = genWdata(io.wdata, size),
+    wmask = genWmask(addr, size), cmd = Mux(isStore, SimpleBusCmd.write, SimpleBusCmd.read))
   dmem.req.valid := valid && (state === s_idle) && !mmio
-  dmem.req.bits.cmd := Mux(isStore, SimpleBusCmd.write, SimpleBusCmd.read)
-  dmem.req.bits.wdata := genWdata(io.wdata, func(1, 0))
-  dmem.req.bits.wmask := genWmask(addr, func(1, 0))
   dmem.resp.ready := true.B
 
   io.mmio.req.bits := dmem.req.bits