fix(cache): fix some problems in 64bit cache, dummy test passed

Makefile

@@ -56,9 +56,9 @@ $(EMU_MK): $(SIM_TOP_V) | $(EMU_DEPS)
 	verilator --cc --exe $(VERILATOR_FLAGS) \
 		-o $(abspath $(EMU)) -Mdir $(@D) $^ $(EMU_DEPS)
 
-REF_SO := $(NEMU_HOME)/build/riscv32-nemu-so
+REF_SO := $(NEMU_HOME)/build/riscv64-nemu-so
 $(REF_SO):
-	$(MAKE) -C $(NEMU_HOME) ISA=riscv32 SHARE=1
+	$(MAKE) -C $(NEMU_HOME) ISA=riscv64 SHARE=1
 
 $(EMU): $(EMU_MK) $(EMU_DEPS) $(EMU_HEADERS) $(REF_SO)
 	CPPFLAGS=-DREF_SO=\\\"$(REF_SO)\\\" $(MAKE) -C $(dir $(EMU_MK)) -f $(abspath $(EMU_MK))

devlog.md

+开发日志
+=================
+
+[TOC]
+
+# CPU调整到riscv64指令集 2019.9.3-
+
+- 调整数据通路宽度到64
+- 调整DCache读写宽度
+- 调整外围内存, 总线配置
+- 引入新指令
+
+## 模块改动说明
+
+### Cache
+
+* Cache64: 64位数据缓存, 使用64位地址
+* 目前所有的Cache对外数据宽度均为64
+
+RV64指令集中, 地址非对齐的访存结果是实现相关的, 为了简化设计, 这里对非对齐的访存不做特殊处理
+
+TODO: IMM变化 1 
+TODO: 32位乘法器/除法器 1
+TODO: RESET VECTOR
+TODO: 64 bit AddressSpace 分配
+TODO: cache直接使用参数改成64位的效果尚未测试
+TODO: 特权寄存器变更
+TODO: simple bus 调整和 AXI4 调整 1
+
+## 新指令列表
+
+```
+指令|模式|当前进度
+---     |BitPat("b1098765_43210_98765_432_10987_6543210")|-
+LWU     |BitPat("b???????_?????_?????_110_?????_0000011")|1
+LD      |BitPat("b???????_?????_?????_011_?????_0000011")|1
+SD      |BitPat("b???????_?????_?????_011_?????_0100011")|1
+SLLI    |BitPat("b0000000_?????_?????_001_?????_0010011")|1
+SRLI    |BitPat("b0000000_?????_?????_101_?????_0010011")|1
+SRAI    |BitPat("b0100000_?????_?????_101_?????_0010011")|1
+ADDIW   |BitPat("b???????_?????_?????_000_?????_0011011")|1
+SLLIW   |BitPat("b0000000_?????_?????_001_?????_0011011")|1
+SRLIW   |BitPat("b0000000_?????_?????_101_?????_0011011")|1
+SRAIW   |BitPat("b0100000_?????_?????_101_?????_0011011")|1
+ADDW    |BitPat("b0000000_?????_?????_000_?????_0111011")|1
+SUBW    |BitPat("b0100000_?????_?????_000_?????_0111011")|1
+SLLW    |BitPat("b0000000_?????_?????_001_?????_0111011")|1
+SRLW    |BitPat("b0000000_?????_?????_101_?????_0111011")|1
+SRAW    |BitPat("b0100000_?????_?????_101_?????_0111011")|1
+
+MULW    |BitPat("b0100000_?????_?????_101_?????_0111011")|1
+DIVW    |BitPat("b0100000_?????_?????_101_?????_0111011")|1
+DIVUW   |BitPat("b0100000_?????_?????_101_?????_0111011")|1
+REMW    |BitPat("b0100000_?????_?????_101_?????_0111011")|1
+REMUW   |BitPat("b0100000_?????_?????_101_?????_0111011")|1
+```
+
+其他要调整的指令
+* LX/SX
+* ALUI
\ No newline at end of file

src/main/scala/bus/simplebus/DistributedMem.scala

@@ -12,15 +12,15 @@ class DistributedMem(memByte: Int, dualPort: Boolean, delayCycles: Int = 0, data
 
   val useTreadle = false
 
-  val wordNum = memByte / 4
+  val wordNum = memByte / 8 
   val memAddrBits = log2Up(wordNum)
   def Index(addr: UInt): UInt = addr(memAddrBits + 2 - 1, 2)
 
   val rwIdx = Index(io.rw.req.bits.addr)
   val roIdx = Index(io.ro.req.bits.addr)
   val wen = io.rw.isWrite()
-  val wdataVec = VecInit.tabulate(4) { i => io.rw.req.bits.wdata(8 * (i + 1) - 1, 8 * i) }
-  val wmask = VecInit.tabulate(4) { i => io.rw.req.bits.wmask(i).toBool }
+  val wdataVec = VecInit.tabulate(8) { i => io.rw.req.bits.wdata(8 * (i + 1) - 1, 8 * i) }
+  val wmask = VecInit.tabulate(8) { i => io.rw.req.bits.wmask(i).toBool }
 
   val rwData = Wire(UInt(64.W))
   val roData = Wire(UInt(64.W))
@@ -29,18 +29,18 @@ class DistributedMem(memByte: Int, dualPort: Boolean, delayCycles: Int = 0, data
     val mem = Mem(memByte, UInt(8.W))
     if (dataFile != "")
       loadMemoryFromFile(mem, dataFile)
-    def read(idx: UInt) = Cat(mem(idx + 3.U), mem(idx + 2.U), mem(idx + 1.U), mem(idx + 0.U))
+    def read(idx: UInt) = Cat(mem(idx + 7.U), mem(idx + 6.U), mem(idx + 5.U), mem(idx + 4.U), mem(idx + 3.U), mem(idx + 2.U), mem(idx + 1.U), mem(idx + 0.U))
 
-    rwData := read(rwIdx << 2)
-    roData := read(roIdx << 2)
+    rwData := read(rwIdx << 3)
+    roData := read(roIdx << 3)
     wmask.zipWithIndex.map { case(m, i) => {
       when (m && wen) {
-        mem((rwIdx << 2) + i.U) := wdataVec(i)
+        mem((rwIdx << 3) + i.U) := wdataVec(i)
       }
     }}
   }
   else {
-    val mem = Mem(wordNum, Vec(4, UInt(8.W)))
+    val mem = Mem(wordNum, Vec(8,  UInt(8.W)))
     if (dataFile != "")
       loadMemoryFromFile(mem, dataFile)
 

src/main/scala/bus/simplebus/ToAXI4.scala

@@ -26,7 +26,7 @@ class SimpleBus2AXI4Converter[IT <: SimpleBusUL, OT <: AXI4Lite]
   w.data := mem.req.bits.wdata
   w.strb := mem.req.bits.wmask
 
-  def LineBeats = 8
+  def LineBeats = 4 //Note: LineBeats = 8 while using rv32 inst set 
   val wlast = WireInit(true.B)
   val rlast = WireInit(true.B)
   if (UHtoAXI4) {

src/main/scala/device/AXI4RAM.scala

@@ -12,22 +12,22 @@ import utils._
 class RAMHelper(memByte: Int) extends BlackBox {
   val io = IO(new Bundle {
     val clk = Input(Clock())
-    val rIdx = Input(UInt(32.W))
-    val rdata = Output(UInt(32.W))
-    val wIdx = Input(UInt(32.W))
-    val wdata = Input(UInt(32.W))
-    val wmask = Input(UInt(32.W))
+    val rIdx = Input(UInt(64.W))
+    val rdata = Output(UInt(64.W))
+    val wIdx = Input(UInt(64.W))
+    val wdata = Input(UInt(64.W))
+    val wmask = Input(UInt(64.W))
     val wen = Input(Bool())
   })
 }
 
-class AXI4RAM[T <: AXI4Lite](_type: T = new AXI4, memByte: Int, beatBytes: Int = 4,
+class AXI4RAM[T <: AXI4Lite](_type: T = new AXI4, memByte: Int, beatBytes: Int = 8,
   useBlackBox: Boolean = false) extends AXI4SlaveModule(_type) {
 
   val offsetBits = log2Up(memByte)
   val offsetMask = (1 << offsetBits) - 1
   def index(addr: UInt) = (addr & offsetMask.U) >> log2Ceil(beatBytes)
-  def inRange(idx: UInt) = idx < (memByte / 4).U
+  def inRange(idx: UInt) = idx < (memByte / 8).U
 
   val wIdx = index(waddr) + writeBeatCnt
   val rIdx = index(raddr) + readBeatCnt

src/main/scala/noop/Cache.scala

@@ -26,7 +26,7 @@ sealed trait HasCacheConst {
     val tag = UInt(TagBits.W)
     val index = UInt(IndexBits.W)
     val wordIndex = UInt(WordIndexBits.W)
-    val byteOffset = UInt(2.W)
+    val byteOffset = UInt(3.W)//rv32: byteOffset = UInt(2.W)
   }
 
   def CacheMetaArrayReadBus() = new SRAMReadBus(new MetaBundle, set = Sets, way = Ways)
@@ -181,7 +181,7 @@ sealed class CacheStage3(ro: Boolean, name: String, userBits: Int = 0) extends M
   io.mem.req.bits.cmd := Mux(state === s_memReadReq, SimpleBusCmd.cmdRead, SimpleBusCmd.cmdWrite)
 
   // critical word first
-  val raddr = Cat(req.addr(63, 2), 0.U(2.W))
+  val raddr = Cat(req.addr(63, 3), 0.U(3.W))
   // dirty block addr
   val waddr = Cat(meta.tag, addr.index, 0.U(OffsetBits.W))
   io.mem.req.bits.addr := Mux(state === s_memReadReq, raddr, waddr)
@@ -203,6 +203,9 @@ sealed class CacheStage3(ro: Boolean, name: String, userBits: Int = 0) extends M
   val readingFirst = !afterFirstRead && io.mem.resp.fire() && (state === s_memReadResp)
   val inRdataRegDemand = RegEnable(io.mem.resp.bits.rdata, readingFirst)
 
+  when(io.mem.req.valid && io.mem.req.ready){
+    printf("[L1$] mem access addr: %x\n", io.mem.req.bits.addr)
+  }
 
   switch (state) {
     is (s_idle) {
@@ -210,7 +213,9 @@ sealed class CacheStage3(ro: Boolean, name: String, userBits: Int = 0) extends M
       alreadyOutFire := false.B
 
       // actually this can use s2 to test
-      when (miss && !req.isUpdate() && !io.flush) { state := Mux(if (ro) false.B else meta.dirty, s_memWriteReq, s_memReadReq) }
+      when (miss && !req.isUpdate() && !io.flush) { 
+        state := Mux(if (ro) false.B else meta.dirty, s_memWriteReq, s_memReadReq) 
+        }
     }
     is (s_memReadReq) { when (io.mem.req.fire()) {
       state := s_memReadResp
@@ -229,6 +234,7 @@ sealed class CacheStage3(ro: Boolean, name: String, userBits: Int = 0) extends M
 
         dataRefillWriteBus.req.bits.data.data := inRdata
         dataRefillWriteBus.req.bits.wordIndex := readBeatCnt.value
+        printf("[L1$] mem access data : %x\n", dataRefillWriteBus.req.bits.data.data)
 
         readBeatCnt.inc()
         when (io.mem.resp.bits.rlast) { state := s_wait_resp }
@@ -268,6 +274,10 @@ sealed class CacheStage3(ro: Boolean, name: String, userBits: Int = 0) extends M
   io.out.bits.rlast := true.B
   io.out.bits.user := io.in.bits.req.user
   io.out.valid := io.in.valid && Mux(hit, !req.isUpdate(), Mux(req.isWrite(), state === s_wait_resp, afterFirstRead && !alreadyOutFire))
+
+  when(io.out.fire()){
+    printf("[L1$] cache return: data:%x\n", io.out.bits.rdata)
+  }
   // With critical-word first, the pipeline registers between
   // s2 and s3 can not be overwritten before a missing request
   // is totally handled. We use io.isFinish to indicate when the

src/main/scala/noop/IFU.scala

@@ -11,7 +11,7 @@ trait HasResetVector {
   val resetVector = 0x80100000L//TODO: set reset vec
 }
 
-class IFU extends Module with HasResetVector {
+class IFU(implicit val p: NOOPConfig) extends Module with HasResetVector {
   val io = IO(new Bundle {
     val imem = new SimpleBusUH(userBits = 32)
     val pc = Input(UInt(64.W))
@@ -39,25 +39,36 @@ class IFU extends Module with HasResetVector {
   //bp2.io.in.bits := io.out.bits
   //bp2.io.in.valid := io.imem.resp.fire()
 
-  when (pcUpdate) { pc := npc }
+  when (pcUpdate) { 
+    pc := npc 
+    // printf("[IF1] pc=%x\n", pc)
+  }
 
   io.flushVec := Mux(io.redirect.valid, "b1111".U, 0.U)
   io.bpFlush := false.B
 
   io.imem := DontCare
   io.imem.req.valid := io.out.ready
-  io.imem.req.bits.addr := Cat(pc(63:3), Fill(3, "b0".U))//inst is 32 bit in length, the right inst will be picked out at stage 3
-  io.imem.req.bits.size := "b10".U
+  io.imem.req.bits.addr := Cat(pc(63,2),0.U(2.W))//cache will treat it as Cat(pc(63,3),0.U(3.W)) 
+  io.imem.req.bits.size := "b11".U
   io.imem.req.bits.cmd := SimpleBusCmd.cmdRead
   io.imem.req.bits.user := npc
   io.imem.resp.ready := io.out.ready || io.flushVec(0)
 
   io.out.bits := DontCare
   io.out.bits.pc := io.pc
-  io.out.bits.instr := Mux(io.pc(2), io.imem.resp.bits.rdata(63,32), io.imem.resp.bits.rdata(31,0))//inst path only uses 32bit inst, get the right inst according to pc(2)
+  if (p.HasIcache) {
+    io.out.bits.instr := Mux(io.pc(2), io.imem.resp.bits.rdata(63,32), io.imem.resp.bits.rdata(31,0))//inst path only uses 32bit inst, get the right inst according to pc(2)
+  }else{
+    io.out.bits.instr := io.imem.resp.bits.rdata(31,0)
+  }
   io.out.bits.pnpc := io.imem.resp.bits.user
   io.out.valid := io.imem.resp.valid && !io.flushVec(0)
 
+  when (io.out.fire()) {
+        printf("[IF1] pc=%x inst=%x\n", io.out.bits.pc, io.out.bits.instr)
+  }
+
   BoringUtils.addSource(BoolStopWatch(io.imem.req.valid, io.imem.resp.fire()), "perfCntCondMimemStall")
   BoringUtils.addSource(io.flushVec.orR, "perfCntCondMifuFlush")
 }

src/main/scala/noop/ISU.scala

@@ -92,5 +92,9 @@ class ISU(implicit val p: NOOPConfig) extends Module {
 
   if (!p.FPGAPlatform) {
     BoringUtils.addSource(VecInit((0 to 31).map(i => rf.read(i.U))), "difftestRegs")
+
+  when(io.out.fire()){
+      printf("[ISU] pc=%x, inst=%x rfwen=%b\n", io.out.bits.cf.pc, io.out.bits.cf.instr, io.out.bits.ctrl.rfWen)
+    }
   }
 }

src/main/scala/noop/WBU.scala

@@ -18,7 +18,10 @@ class WBU(implicit val p: NOOPConfig) extends Module {
 
   io.redirect := io.in.bits.decode.cf.redirect
   io.redirect.valid := io.in.bits.decode.cf.redirect.valid && io.in.valid
-
+  
+  when(io.wb.rfWen){
+    printf("[WBU] pc:%x reg: %d, data: %x\n", io.in.bits.decode.cf.pc, io.wb.rfDest, io.wb.rfData)
+  }
   BoringUtils.addSource(io.in.valid, "perfCntCondMinstret")
   if (!p.FPGAPlatform) {
     BoringUtils.addSource(RegNext(io.in.valid), "difftestCommit")

src/main/scala/noop/fu/ALU.scala

@@ -101,7 +101,7 @@ object ALUInstr extends HasInstrType {
     SRLW           -> List(InstrR, FuType.alu, ALUOpType.srlw),
     SRAW           -> List(InstrR, FuType.alu, ALUOpType.sraw),
     ADDW            -> List(InstrR, FuType.alu, ALUOpType.addw),
-    SUBW            -> List(InstrR, FuType.alu, ALUOpType.subw),
+    SUBW            -> List(InstrR, FuType.alu, ALUOpType.subw)
 
   )
 }
@@ -124,8 +124,8 @@ class ALU extends Module {
     io.out.bits
   }
 
-  val src132 = src1(31:0)
-  val src232 = src2(31:0)
+  val src132 = src1(31,0)
+  val src232 = src2(31,0)
 
   val isAdderSub = (func =/= ALUOpType.add) && (func =/= ALUOpType.addw) && !BRUOpType.isJump(func)
   val adderRes = (src1 +& (src2 ^ Fill(64, isAdderSub))) + isAdderSub
@@ -143,11 +143,11 @@ class ALU extends Module {
     ALUOpType.sllw -> Cat(Fill(32, (src132  << shamt)(31)), (src132  << shamt)(31, 0)),
     ALUOpType.xor  -> xorRes,
     ALUOpType.srl  -> (src1  >> shamt64),
-    ALUOpType.srlw -> Cat(Fill(32, (src132  >> shamt)(31)), (src132  >> shamt)(31:0)),
+    ALUOpType.srlw -> Cat(Fill(32, (src132  >> shamt)(31)), (src132  >> shamt)(31,0)),
     ALUOpType.or   -> (src1  |  src2),
     ALUOpType.and  -> (src1  &  src2),
     ALUOpType.sra  -> ((src1.asSInt >> shamt64).asUInt),
-    ALUOpType.sraw -> Cat(Fill(32, ((src132.asSInt >> shamt).asUInt)(31)), ((src132.asSInt >> shamt).asUInt)(31:0)),
+    ALUOpType.sraw -> Cat(Fill(32, (src132.asSInt >> shamt)(31)), ((src132.asSInt >> shamt).asUInt)),
     ALUOpType.addw -> adderWRes
   ))
 

src/main/scala/noop/fu/LSU.scala

@@ -46,7 +46,7 @@ object LSUInstr extends HasInstrType {
     LHU            -> List(InstrI, FuType.lsu, LSUOpType.lwu),
     SB             -> List(InstrS, FuType.lsu, LSUOpType.sb ),
     SH             -> List(InstrS, FuType.lsu, LSUOpType.sh ),
-    SW             -> List(InstrS, FuType.lsu, LSUOpType.sw)
+    SW             -> List(InstrS, FuType.lsu, LSUOpType.sw),
     SD             -> List(InstrS, FuType.lsu, LSUOpType.sd)
   )
 }
@@ -123,6 +123,9 @@ class LSU extends Module {
   io.mmio.req.valid := valid && (state === s_idle) && mmio
   io.mmio.resp.ready := true.B
 
+  when(dmem.req.fire()){
+    printf("[LSU] addr:%x data:%x wen:%b\n",addr, dmem.req.bits.wdata, isStore)
+  } 
   io.out.valid := Mux(isStore && !mmio, state === s_partialLoad, Mux(partialLoad, state === s_partialLoad,
     Mux(mmio, io.mmio.resp.fire(), dmem.resp.fire() && (state === s_wait_resp))))
   io.in.ready := (state === s_idle)
@@ -134,7 +137,7 @@ class LSU extends Module {
     "b000".U -> rdataLatch(63, 0),
     "b001".U -> rdataLatch(63, 8),
     "b010".U -> rdataLatch(63, 16),
-    "b011".U -> rdataLatch(63, 24)
+    "b011".U -> rdataLatch(63, 24),
     "b100".U -> rdataLatch(63, 32),
     "b101".U -> rdataLatch(63, 40),
     "b110".U -> rdataLatch(63, 48),
@@ -145,7 +148,7 @@ class LSU extends Module {
       LSUOpType.lh   -> Cat(Fill(16+32, rdataSel(15)), rdataSel(15, 0)),
       LSUOpType.lw   -> Cat(Fill(32, rdataSel(31)), rdataSel(32, 0)),
       LSUOpType.lbu  -> Cat(0.U((24+32).W), rdataSel(7, 0)),
-      LSUOpType.lhu  -> Cat(0.U((16+32).W), rdataSel(15, 0))
+      LSUOpType.lhu  -> Cat(0.U((16+32).W), rdataSel(15, 0)),
       LSUOpType.lwu  -> Cat(0.U((32).W), rdataSel(32, 0))
   ))
 

src/main/scala/noop/fu/MDU.scala

@@ -32,10 +32,11 @@ object MDUInstr extends HasInstrType {
   def DIVU    = BitPat("b0000001_?????_?????_101_?????_0110011")
   def REM     = BitPat("b0000001_?????_?????_110_?????_0110011")
   def REMU    = BitPat("b0000001_?????_?????_111_?????_0110011")
-  def DIVW    = BitPat("b0100000_?????_?????_101_?????_0111011")
-  def DIVUW   = BitPat("b0100000_?????_?????_101_?????_0111011")
-  def REMW    = BitPat("b0100000_?????_?????_101_?????_0111011")
-  def REMUW   = BitPat("b0100000_?????_?????_101_?????_0111011")
+  def MULW    = BitPat("b0000001_?????_?????_000_?????_0111011")
+  def DIVW    = BitPat("b0000001_?????_?????_100_?????_0111011")
+  def DIVUW   = BitPat("b0000001_?????_?????_101_?????_0111011")
+  def REMW    = BitPat("b0000001_?????_?????_110_?????_0111011")
+  def REMUW   = BitPat("b0000001_?????_?????_111_?????_0111011")
 
   val mulTable = Array(
     MUL            -> List(InstrR, FuType.mdu, MDUOpType.mul),
@@ -148,8 +149,8 @@ class MDU(implicit val p: NOOPConfig) extends Module {
     x.out.ready := io.out.ready
   }
   List(mul32.io, div32.io).map { case x =>
-    x.in.bits(0) := src1(31:0)
-    x.in.bits(1) := src2(31:0)
+    x.in.bits(0) := src1(31,0)
+    x.in.bits(1) := src2(31,0)
     x.sign := MDUOpType.isSign(func)
     x.out.ready := io.out.ready
   }

src/test/csrc/device.cpp

@@ -10,7 +10,7 @@ uint32_t screen_size(void);
 void set_abort(void);
 
 static struct timeval boot = {};
-static uint32_t vmem[0x400000 / sizeof(uint32_t)];
+static uint64_t vmem[0x400000 / sizeof(uint64_t)];
 
 void init_device(void) {
   init_sdl();
@@ -51,7 +51,7 @@ uint32_t uptime(void) {
 }
 
 extern "C" void device_helper(
-    uint8_t req_wen, uint32_t req_addr, uint32_t req_wdata, uint8_t req_wmask, uint32_t *resp_rdata) {
+    uint8_t req_wen, uint64_t req_addr, uint64_t req_wdata, uint8_t req_wmask, uint64_t *resp_rdata) {
   switch (req_addr) {
       // read uartlite stat register
     case 0x40600008:
@@ -70,7 +70,7 @@ extern "C" void device_helper(
     default:
       if (req_addr >= 0x40000000 && req_addr < 0x40400000 && req_wen) {
         // write to vmem
-        vmem[(req_addr - 0x40000000) / sizeof(uint32_t)] = req_wdata;
+        vmem[(req_addr - 0x40000000) / sizeof(uint64_t)] = req_wdata;
       }
       else {
         eprintf("bad address = 0x%08x, wen = %d\n", req_addr, req_wen);

src/test/csrc/difftest.cpp

@@ -33,7 +33,7 @@ void difftest_skip_dut() {
   is_skip_dut = true;
 }
 
-void init_difftest(uint32_t *reg, const char *mainargs) {
+void init_difftest(uint64_t *reg, const char *mainargs) {
   void *handle;
   handle = dlopen(REF_SO, RTLD_LAZY | RTLD_DEEPBIND);
   assert(handle);
@@ -64,11 +64,11 @@ void init_difftest(uint32_t *reg, const char *mainargs) {
   ref_difftest_setregs(reg);
 }
 
-int difftest_step(uint32_t *reg_scala, uint32_t this_pc, int isMMIO) {
-  uint32_t ref_r[33];
-  static uint32_t nemu_pc = 0x80100000;
-
+int difftest_step(uint64_t *reg_scala, uint64_t this_pc, int isMMIO) {
+  uint64_t ref_r[33];
+  static uint64_t nemu_pc = 0x80100000;
   if (isMMIO) {
+printf("diff pc: %x\n", this_pc);
     // MMIO accessing should not be a branch or jump, just +4 to get the next pc
     reg_scala[32] += 4;
     nemu_pc += 4;
@@ -80,7 +80,7 @@ int difftest_step(uint32_t *reg_scala, uint32_t this_pc, int isMMIO) {
   ref_difftest_exec(1);
   ref_difftest_getregs(&ref_r);
 
-  uint32_t temp = ref_r[32];
+  uint64_t temp = ref_r[32];
   ref_r[32] = nemu_pc;
   nemu_pc = temp;
 

src/test/csrc/difftest.h

@@ -5,10 +5,10 @@
 #include <assert.h>
 #include <string.h>
 
-typedef uint32_t rtlreg_t;
+typedef uint64_t rtlreg_t;
 
-typedef uint32_t paddr_t;
-typedef uint32_t vaddr_t;
+typedef uint64_t paddr_t;
+typedef uint64_t vaddr_t;
 
 typedef uint16_t ioaddr_t;
 

src/test/csrc/emu.h

@@ -24,7 +24,7 @@ class Emulator {
   static const struct option long_options[];
   static void print_help(const char *file);
 
-  void read_emu_regs(uint32_t *r) {
+  void read_emu_regs(uint64_t *r) {
 #define macro(x) r[x] = dut_ptr->io_difftest_r_##x
     macro(0); macro(1); macro(2); macro(3); macro(4); macro(5); macro(6); macro(7);
     macro(8); macro(9); macro(10); macro(11); macro(12); macro(13); macro(14); macro(15);
@@ -60,8 +60,8 @@ class Emulator {
     // init core
     reset_ncycles(10);
 
-    extern void init_difftest(uint32_t *reg, const char *mainargs);
-    uint32_t reg[33];
+    extern void init_difftest(uint64_t *reg, const char *mainargs);
+    uint64_t reg[33];
     read_emu_regs(reg);
     reg[32] = 0x80100000;
     init_difftest(reg, mainargs);
@@ -108,10 +108,10 @@ class Emulator {
 
       // difftest
       if (dut_ptr->io_difftest_commit) {
-        uint32_t reg[33];
+        uint64_t reg[33];
         read_emu_regs(reg);
 
-        extern int difftest_step(uint32_t *reg_scala, uint32_t this_pc, int isMMIO);
+        extern int difftest_step(uint64_t *reg_scala, uint64_t this_pc, int isMMIO);
         if (difftest_step(reg, dut_ptr->io_difftest_thisPC, dut_ptr->io_difftest_isMMIO)) {
           set_abort();
         }

src/test/csrc/monitor.cpp

@@ -8,12 +8,12 @@ enum {
 };
 
 static int g_trapCode = STATE_RUNNING;
-static int g_trapPC = 0;
+static uint64_t g_trapPC = 0;
 static int g_cycleCnt = 0, g_instrCnt = 0;
 
 bool is_finish() { return g_trapCode != STATE_RUNNING; }
 
-extern "C" void monitor(int trapCode, int trapPC, int cycleCnt, int instrCnt) {
+extern "C" void monitor(int trapCode, uint64_t trapPC, int cycleCnt, int instrCnt) {
   g_trapCode = trapCode;
   g_trapPC = trapPC;
   g_cycleCnt = cycleCnt;

src/test/csrc/ram.cpp

@@ -2,9 +2,9 @@
 
 #define RAMSIZE (128 * 1024 * 1024)
 
-static uint32_t ram[RAMSIZE / sizeof(uint32_t)];
+static uint64_t ram[RAMSIZE / sizeof(uint64_t)];
 static long img_size = 0;
-void* get_img_start() { return &ram[0x100000 / sizeof(uint32_t)]; }
+void* get_img_start() { return &ram[0x100000 / sizeof(uint64_t)]; }
 long get_img_size() { return img_size; }
 
 void init_ram(const char *img, const char *mainargs) {
@@ -29,7 +29,7 @@ void init_ram(const char *img, const char *mainargs) {
 }
 
 extern "C" void ram_helper(
-    uint32_t rIdx, uint32_t *rdata, uint32_t wIdx, uint32_t wdata, uint32_t wmask, uint8_t wen) {
+    uint64_t rIdx, uint64_t *rdata, uint64_t wIdx, uint64_t wdata, uint64_t wmask, uint8_t wen) {
   *rdata = ram[rIdx];
   if (wen) { ram[wIdx] = (ram[wIdx] & ~wmask) | (wdata & wmask); }
 }

src/test/scala/top/SimMMIO.scala

@@ -11,10 +11,10 @@ class DeviceHelper extends BlackBox {
     val reset = Input(Bool())
     val reqValid = Input(Bool())
     val reqWen = Input(Bool())
-    val reqAddr = Input(UInt(32.W))
-    val reqWdata = Input(UInt(32.W))
-    val reqWmask = Input(UInt(4.W))
-    val respRdata = Output(UInt(32.W))
+    val reqAddr = Input(UInt(64.W))
+    val reqWdata = Input(UInt(64.W))
+    val reqWmask = Input(UInt(8.W))
+    val respRdata = Output(UInt(64.W))
   })
 }
 

src/test/vsrc/device.v

 import "DPI-C" function void device_helper
 (
   input  bit    req_wen,
-  input  int    req_addr,
-  input  int    req_wdata,
+  input  longint    req_addr,
+  input  longint    req_wdata,
   input  byte   req_wmask,
-  output int    resp_rdata
+  output longint    resp_rdata
 );
 
 module DeviceHelper(
@@ -12,14 +12,14 @@ module DeviceHelper(
   input         reset,
   input         reqValid,
   input         reqWen,
-  input  [31:0] reqAddr,
-  input  [31:0] reqWdata,
-  input  [3:0]  reqWmask,
-  output [31:0] respRdata
+  input  [63:0] reqAddr,
+  input  [63:0] reqWdata,
+  input  [7:0]  reqWmask,
+  output [63:0] respRdata
 );
 
   always @(posedge clk) begin
-    if (reqValid && !reset) device_helper(reqWen, reqAddr, reqWdata, {4'b0, reqWmask}, respRdata);
+    if (reqValid && !reset) device_helper(reqWen, reqAddr, reqWdata, reqWmask, respRdata);
   end
 
 endmodule

src/test/vsrc/monitor.v

@@ -2,7 +2,7 @@
 import "DPI-C" function void monitor
 (
   input  int  trapCode,
-  input  int  trapPC,
+  input  longint  trapPC,
   input  int  cycleCnt,
   input  int  instrCnt
 );
@@ -13,7 +13,7 @@ module Monitor(
   input         reset,
   input         isNoopTrap,
   input  [31:0] trapCode,
-  input  [31:0] trapPC,
+  input  [63:0] trapPC,
   input  [31:0] cycleCnt,
   input  [31:0] instrCnt
 );

src/test/vsrc/ram.v

 import "DPI-C" function void ram_helper
 (
-  input  int    rIdx,
-  output int    rdata,
-  input  int    wIdx,
-  input  int    wdata,
-  input  int    wmask,
+  input  longint    rIdx,
+  output longint    rdata,
+  input  longint    wIdx,
+  input  longint    wdata,
+  input  longint    wmask,
   input  bit    wen
 );
 
 module RAMHelper(
   input         clk,
-  input  [31:0] rIdx,
-  output [31:0] rdata,
-  input  [31:0] wIdx,
-  input  [31:0] wdata,
-  input  [31:0] wmask,
+  input  [63:0] rIdx,
+  output [63:0] rdata,
+  input  [63:0] wIdx,
+  input  [63:0] wdata,
+  input  [63:0] wmask,
   input         wen
 );