noop,BPU: also delay one cycle to update BTB

* Note that at the time of flushing, we also access BTB to predict the
  npc of the redirected target instruction. After the delay update of
  this patch, it will cause a read write conflict for the single-port
  SRAM. Therefore we disable the prediction of the redirected target
  instruction. This will reduce the IPC: 0.544548 -> 0.543382

src/main/scala/noop/BPU.scala

@@ -80,6 +80,7 @@ class BPU1 extends Module with HasBRUOpType {
   val req = WireInit(0.U.asTypeOf(new BPUUpdateReq))
   val btbWrite = WireInit(0.U.asTypeOf(btbEntry))
   BoringUtils.addSink(req, "bpuUpdateReq")
+
   btbWrite.tag := btbAddr.getTag(req.pc)
   btbWrite.target := req.actualTarget
   btbWrite._type := req.btbType
@@ -94,9 +95,8 @@ class BPU1 extends Module with HasBRUOpType {
   btb.io.w.wordIndex := 0.U // ???
   btb.io.w.entry := btbWrite
 
-  val reqLatch = RegNext(req)
-  when (reqLatch.valid && isBranch(reqLatch.fuOpType)) {
-    pht.write(btbAddr.getIdx(reqLatch.pc), reqLatch.actualTaken)
+  when (req.valid && isBranch(req.fuOpType)) {
+    pht.write(btbAddr.getIdx(req.pc), req.actualTaken)
   }
   when (req.valid) {
     when (req.fuOpType === BruCall) {

src/main/scala/noop/IFU.scala

@@ -29,9 +29,9 @@ class IFU extends Module with HasResetVector {
   val bp1 = Module(new BPU1)
   // predicted next pc
   val pnpc = bp1.io.out.target
-  val npc = Mux(io.br.isTaken, io.br.target, Mux(bp1.io.out.isTaken, pnpc, snpc))
+  val npc = Mux(io.br.isTaken, io.br.target, Mux(bp1.io.out.isTaken && !RegNext(io.br.isTaken), pnpc, snpc))
 
-  bp1.io.in.pc.valid := pcUpdate // only predict when pc is updated
+  bp1.io.in.pc.valid := io.imem.req.fire() // only predict when Icache accepts a request
   bp1.io.in.pc.bits := npc  // predict one cycle early
 
   val bp2 = Module(new BPU2)

src/main/scala/noop/fu/BRU.scala

@@ -109,7 +109,7 @@ class BRU extends Module with HasBRUOpType {
   bpuUpdateReq.fuOpType := func
   bpuUpdateReq.btbType := LookupTree(func, BRUInstr.bruFuncTobtbTypeTable)
 
-  BoringUtils.addSource(bpuUpdateReq, "bpuUpdateReq")
+  BoringUtils.addSource(RegNext(bpuUpdateReq), "bpuUpdateReq")
 
   val right = valid && (io.npc === io.branch.target)
   val wrong = valid && (io.npc =/= io.branch.target)