1. 06 9月, 2021 1 次提交
  2. 05 9月, 2021 4 次提交
  3. 04 9月, 2021 1 次提交
  4. 03 9月, 2021 3 次提交
  5. 02 9月, 2021 4 次提交
    • L
      l0tlb: add a new level tlb, a load tlb and a store tlb (#961) · a0301c0d
      Lemover 提交于
      * Revert "Revert "l0tlb: add a new level tlb to each mem pipeline (#936)" (#945)"
      
      This reverts commit b052b972.
      
      * fu: remove unused import
      
      * mmu.tlb: 2 load/store pipeline has 1 dtlb
      
      * mmu: remove btlb, the l1-tlb
      
      * mmu: set split-tlb to 32 to check perf effect
      
      * mmu: wrap tlb's param with TLBParameters
      
      * mmu: add params 'useBTlb'
      
      dtlb size is small: normal 8, super 2
      
      * mmu.tlb: add Bundle TlbEntry, simplify tlb hit logic(coding)
      
      * mmu.tlb: seperate tlb's storage, relative hit/sfence logic
      
      tlb now supports full-associate, set-associate, directive-associate.
      more: change tlb's parameter usage, change util.Random to support
      case that mod is 1.
      
      * mmu.tlb: support normalAsVictim, super(fa) -> normal(sa/da)
      
      be carefull to use tlb's parameter, only a part of param combination
      is supported
      
      * mmu.tlb: fix bug of hit method and victim write
      
      * mmu.tlb: add tlb storage's perf counter
      
      * mmu.tlb: rewrite replace part, support set or non-set
      
      * mmu.tlb: add param outReplace to receive out replace index
      
      * mmu.tlb: change param superSize to superNWays
      
      add param superNSets, which should always be 1
      
      * mmu.tlb: change some perf counter's name and change some params
      
      * mmu.tlb: fix bug of replace io bundle
      
      * mmu.tlb: remove unused signal wayIdx in tlbstorageio
      
      * mmu.tlb: separate tlb_ld/st into two 'same' tlb
      
      * mmu.tlb: when nWays is 1, replace returns 0.U
      
      before, replace will return 1.U, no influence for refill but bad
      for perf counter
      
      * mmu.tlb: give tlb_ld and tlb_st a name (in waveform)
      a0301c0d
    • W
      chore: fix frontend / memblock merge conflict · 154904ce
      William Wang 提交于
      154904ce
    • Y
      rs,mem: support fast load-to-load wakeup and issue (#984) · 718f8a60
      Yinan Xu 提交于
      This PR adds support for fast load-to-load wakeup and issue. In load-to-load fast wakeup and issue, load-to-load latency is reduced to 2 cycles.
      
      Now a load instruction can wakeup another load instruction at LOAD stage 1. When the producer load instruction arrives at stage 2, the consumer load instruction is issued to load stage 0 and using data from the producer to generate load address.
      
      In reservation station, load can be dequeued from staged 1 when stage 2 does not have a valid instruction. If the fast load is not accepted, from the next cycle on, the load will dequeue as normal.
      
      Timing in reservation station (for imm read) and load unit (for writeback data selection) to be optimized later.
      
      * backend,rs: issue load one cycle earlier when possible
      
      This commit adds support for issuing load instructions one cycle
      earlier if the load instruction is wakeup by another load. An extra
      2-bit UInt is added to IO.
      
      * mem: add load to load addr fastpath framework
      
      * mem: enable load to load forward
      
      * mem: add load-load forward counter
      Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>
      718f8a60
    • Y
      Rename: fix doAllocate logic in refactored version · 4efb89cb
      YikeZhou 提交于
      MEFreeList: remove useless code + give specified
      (instead of DontCare) value to phy reg allocated port
      4efb89cb
  6. 01 9月, 2021 10 次提交
  7. 31 8月, 2021 4 次提交
    • J
      fudian: The new floating-point lib to replace hardfloat (#975) · dc597826
      Jiawei Lin 提交于
      * Add submodule 'fudian'
      
      * IntToFP: use fudian
      
      * FMA: use fudian.CMA
      
      * FPToInt: remove recode format
      dc597826
    • L
    • Z
      Alu: optimize timing for bitmanip (#979) · 28c18878
      zfw 提交于
      * Alu: optimize timing
      
      This pull request optimizes timing by adding a 32bit adder for addw and changing the encode.
      28c18878
    • Y
      backend,exu: connect writeback when possible (#977) · dd381594
      Yinan Xu 提交于
      This commit optimizes ExuBlock timing by connecting writeback when
      possible.
      
      The timing priorities are RegNext(rs.fastUopOut) > fu.writeback >
      arbiter.out(--> io.rfWriteback --> rs.writeback). The higher priority,
      the better timing.
      
      (1) When function units have exclusive writeback ports, their
      wakeup ports for reservation stations can be connected directly from
      function units' writeback ports. Special case: when the function unit
      has fastUopOut, valid and uop should be RegNext.
      
      (2) If the reservation station has fastUopOut for all instructions
      in this exu, we should replace io.fuWriteback with RegNext(fastUopOut).
      In this case, the corresponding execution units must have exclusive
      writeback ports, unless it's impossible that rs can ensure the
      instruction is able to write the regfile.
      
      (3) If the reservation station has fastUopOut for all instructions in
      this exu, we should replace io.rfWriteback (rs.writeback) with
      RegNext(rs.wakeupOut).
      dd381594
  8. 30 8月, 2021 3 次提交
  9. 29 8月, 2021 2 次提交
    • L
      l2tlb: mem access now takes 512 bits, 8 ptes (#973) · 5854c1ed
      Lemover 提交于
      * mmu: wrap l2tlb's param withL2TLBParameters
      
      * mmu.l2tlb: add param blockBytes: 64, 8 ptes
      
      * mmu.l2tlb: set l2tlb cache size to l2:256, l3:4096
      
      * mmu.l2tlb: add config print
      
      * mmu.l2tlb: fix bug of resp data indices choosen and opt coding style
      5854c1ed
    • Y
      rs,bypass: add left and right bypass strategy (#971) · 605f31fc
      Yinan Xu 提交于
      * rs,bypass: remove optBuf for valid bits
      
      * rs,bypass: add left and right bypass strategy
      
      This commit adds another bypass network implementation to optimize timing of the first stage of function units.
      
      In BypassNetworkLeft, we bypass data at the same cycle that function units write data back. This increases the length of the critical path of the last stage of function units but reduces the length of the critical path of the first stage of function units. Some function units that require a shorter stage zero, like LOAD, may use BypassNetworkLeft.
      
      In this commit, we set all bypass networks to the left style, but we will make it configurable depending on different function units in the future.
      605f31fc
  10. 28 8月, 2021 4 次提交
  11. 27 8月, 2021 4 次提交
    • L
      ftq: add perf counter for predecode redirect · c92646b5
      Lingrui98 提交于
      c92646b5
    • Y
      rs,age: use less registers for age matrix (#964) · 38683dba
      Yinan Xu 提交于
      This commit reduces register usage in age detector via using the
      upper matrix only. Since the age matrix is symmetric, age(i)(j)
      equals !age(j)(i). Besides, age(i)(i) is the same as valid(i).
      Thus, we also remove validVec in this commit.
      38683dba
    • Y
      backend,fu: allow early arbitration via fastUopOut (#962) · f83b578a
      Yinan Xu 提交于
      This commit adds a fastUopOut option to function units. This allows the
      function units to give valid and uop one cycle before its output data is
      ready. FastUopOut lets writeback arbitration happen one cycle before
      data is ready and helps optimize the timing.
      
      Since some function units are not ready for this new feature, this
      commit adds a fastImplemented option to allow function units to have
      fastUopOut but the data is still at the same cycle as uop. This option
      will delay the data for one cycle and may cause performance degradation.
      FastImplemented should be true after function units support fastUopOut.
      f83b578a
    • L
      ftb, ubtb: only store lower bits of target · e6231032
      Lingrui98 提交于
      e6231032