* backend, rename: support elimination of mv inst whose lsrc=0
[known bug] instr page fault not properly raised after sfence.vma

* backend, roq: [bug fix] won't label me with exception as writebacked

This commit adds support for load balance between different issue ports
when the function unit is not pipelined and the reservation station has
more than one issue ports.

We use a ping pong bit to decide which port to issue the instruction. At
every clock cycle, the bit is flipped.

* mmu.l2tlb: l2tlb now support multiple parallel mem accesses

8 missqueue entry and 1 page table worker
mq entry only supports page leaf entry
ptw supports all the three level entries

* mmu.tlb: fix bug of mq.refill_vpn and out.ready

This commit adds assertion in MaskData to check the width of mask
and data. When the width of mask is smaller than the width of data,
(~mask & data) and (mask & data) will always clear the upper bits
of the data. This usually causes unexpected behavior.

This commit adds explicit width declarations where MaskData is used.

* Makefile: add '--gen-mem-verilog'

* FMA: spearate fadd/fmul/fma

* exu: enable fast uop out from fmacExeUnit
Co-authored-by: NYinan Xu <xuyinan@ict.ac.cn>

* Multiplier: adjust pipeline

mem: use vaddr based store to load forward for better timing

This commit adds an 8-entry buffer for fdivSqrt function unit input.
Set hasInputBuffer to true to enable input buffers for other function
units.

* Revert "Revert "l0tlb: add a new level tlb to each mem pipeline (#936)" (#945)"

This reverts commit b052b972.

* fu: remove unused import

* mmu.tlb: 2 load/store pipeline has 1 dtlb

* mmu: remove btlb, the l1-tlb

* mmu: set split-tlb to 32 to check perf effect

* mmu: wrap tlb's param with TLBParameters

* mmu: add params 'useBTlb'

dtlb size is small: normal 8, super 2

* mmu.tlb: add Bundle TlbEntry, simplify tlb hit logic(coding)

* mmu.tlb: seperate tlb's storage, relative hit/sfence logic

tlb now supports full-associate, set-associate, directive-associate.
more: change tlb's parameter usage, change util.Random to support
case that mod is 1.

* mmu.tlb: support normalAsVictim, super(fa) -> normal(sa/da)

be carefull to use tlb's parameter, only a part of param combination
is supported

* mmu.tlb: fix bug of hit method and victim write

* mmu.tlb: add tlb storage's perf counter

* mmu.tlb: rewrite replace part, support set or non-set

* mmu.tlb: add param outReplace to receive out replace index

* mmu.tlb: change param superSize to superNWays

add param superNSets, which should always be 1

* mmu.tlb: change some perf counter's name and change some params

* mmu.tlb: fix bug of replace io bundle

* mmu.tlb: remove unused signal wayIdx in tlbstorageio

* mmu.tlb: separate tlb_ld/st into two 'same' tlb

* mmu.tlb: when nWays is 1, replace returns 0.U

before, replace will return 1.U, no influence for refill but bad
for perf counter

* mmu.tlb: give tlb_ld and tlb_st a name (in waveform)

backend, rename: configurable free list & `headPtr` bug fix & `dst=0/dst=src` move inst elimination

merge decoupled frontend into master

This PR adds support for fast load-to-load wakeup and issue. In load-to-load fast wakeup and issue, load-to-load latency is reduced to 2 cycles.

Now a load instruction can wakeup another load instruction at LOAD stage 1. When the producer load instruction arrives at stage 2, the consumer load instruction is issued to load stage 0 and using data from the producer to generate load address.

In reservation station, load can be dequeued from staged 1 when stage 2 does not have a valid instruction. If the fast load is not accepted, from the next cycle on, the load will dequeue as normal.

Timing in reservation station (for imm read) and load unit (for writeback data selection) to be optimized later.

* backend,rs: issue load one cycle earlier when possible

This commit adds support for issuing load instructions one cycle
earlier if the load instruction is wakeup by another load. An extra
2-bit UInt is added to IO.

* mem: add load to load addr fastpath framework

* mem: enable load to load forward

* mem: add load-load forward counter
Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>

MEFreeList: remove useless code + give specified
(instead of DontCare) value to phy reg allocated port

sbuffer: add perf conuter

config: remove MinimalSimConfigForFetch

bundle: code clean ups

bundle, xscore: code clean ups

* IntToFP: support fully pipelined mode

This reverts commit e3f759ae.

This commit adds fastUopOut support for pipelined function units via
implementing fastUopOut in trait HasPipelineReg.

The following function units now support fastUopOut:
- MUL
- FMA
- F2I
- F2F

* Add submodule 'fudian'

* IntToFP: use fudian

* FMA: use fudian.CMA

* FPToInt: remove recode format

* Alu: optimize timing

This pull request optimizes timing by adding a 32bit adder for addw and changing the encode.

This commit optimizes ExuBlock timing by connecting writeback when
possible.

The timing priorities are RegNext(rs.fastUopOut) > fu.writeback >
arbiter.out(--> io.rfWriteback --> rs.writeback). The higher priority,
the better timing.

(1) When function units have exclusive writeback ports, their
wakeup ports for reservation stations can be connected directly from
function units' writeback ports. Special case: when the function unit
has fastUopOut, valid and uop should be RegNext.

(2) If the reservation station has fastUopOut for all instructions
in this exu, we should replace io.fuWriteback with RegNext(fastUopOut).
In this case, the corresponding execution units must have exclusive
writeback ports, unless it's impossible that rs can ensure the
instruction is able to write the regfile.

(3) If the reservation station has fastUopOut for all instructions in
this exu, we should replace io.rfWriteback (rs.writeback) with
RegNext(rs.wakeupOut).