- 04 6月, 2021 1 次提交
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由 Lemover 提交于
In this commit, we add License for XiangShan project.
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- 11 5月, 2021 1 次提交
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由 William Wang 提交于
* LoadQueue: send stFtqIdx via rollback request * It will make it possible for setore set to update its SSIT * StoreSet: setup store set update req * StoreSet: add store set identifier table (SSIT) * StoreSet: add last fetched store table (LFST) * StoreSet: put SSIT into decode stage * StoreSet: put LFST into dispatch1 * Future work: optimize timing * RS: store rs now supports delayed issue * StoreSet: add perf counter * StoreSet: fix SSIT update logic * StoreSet: delay LFST update input for 1 cycle * StoreSet: fix LFST update logic * StoreSet: fix LFST raddr width * StoreSet: do not force store in ss issue in order Classic store set requires store in the same store set issue in seq. However, in current micro-architecture, such restrict will lead to severe perf lost. We choose to disable it until we find another way to fix it. * StoreSet: support ooo store in the same store set * StoreSet: fix store set merge logic * StoreSet: check earlier store when read LFST * If store-load pair is in the same dispatch bundle, loadWaitBit should also be set for load * StoreSet: increase default SSIT flush period * StoreSet: fix LFST read logic * Fix commit c0e541d1 * StoreSet: add StoreSetEnable parameter * RSFeedback: add source type * StoreQueue: split store addr and store data * StoreQueue: update ls forward logic * Now it supports splited addr and data * Chore: force assign name for load/store unit * RS: add rs'support for store a-d split * StoreQueue: fix stlf logic * StoreQueue: fix addr wb sq update logic * AtomicsUnit: support splited a/d * Parameters: disable store set by default * WaitTable: wait table will not cause store delay * WaitTable: recover default reset period to 2^17 * Fix dev-stad merge conflict * StoreSet: enable storeset * RS: disable store rs delay logic CI perf shows that current delay logic will cause perf loss. Disable unnecessary delay logic will help. To be more specific, `io.readyVec` caused the problem. It will be updated in future commits. * RS: opt select logic with load delay (ldWait) * StoreSet: disable 2-bit lwt Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn>
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- 19 4月, 2021 1 次提交
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由 Jiawei Lin 提交于
* difftest: use DPI-C to refactor difftest In this commit, difftest is refactored with DPI-C calls. There're a few reasons: (1) From Verilator's manual, DPI-C calls should be more efficient than accessing from dut_ptr. (2) DPI-C is cross-platform (Verilator, VCS, ...) (3) difftest APIs are splited from emu.cpp to possibly support more backend platforms (NEMU, Spike, ...) The performance at this commit is quite slower than the original emu. Performance issues will be fixed later. * [WIP] SimTop: try to use 'XSTop' as soc * CircularQueuePtr: ues F-bounded polymorphis instead implict helper * Refactor parameters & Clean up code * difftest: support basic difftest * Support diffetst in new sim top * Difftest; convert recode fmt to ieee754 when comparing fp regs * Difftest: pass sign-ext pc to dpic functions && fix exception pc * Debug: add int/exc inst wb to debug queue * Difftest: pass sign-ext pc to dpic functions && fix exception pc * Difftest: fix naive commit num limit Co-authored-by: NYinan Xu <xuyinan1997@gmail.com> Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>
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- 31 3月, 2021 1 次提交
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由 wakafa 提交于
* csr: remove unused input perfcnt io * perfcnt: add some in-core hardware performance counters * perfcnt: optimize timing for hardware performance counters
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- 11 3月, 2021 1 次提交
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由 Yinan Xu 提交于
In this commit, we add support for a simpler version of move elimination. The original instruction sequences are: move r1, r0 add r2, r1, r3 The optimized sequnces are: move pr1, pr0 add pr2, pr0, pr3 # instead of add pr2, pr1, pr3 In this way, add can be issued once r0 is ready and move seems to be eliminated.
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- 05 3月, 2021 1 次提交
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由 Yinan Xu 提交于
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- 04 3月, 2021 1 次提交
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由 ljw 提交于
* Ftq: save 'hist' in regs * Ftq: save 'br_mask' in regs
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- 02 3月, 2021 1 次提交
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由 ljw 提交于
* CtrlBlock: delay exception flush for 1 cycle * CtrlBlock: delay load replay for 1 cycle * roq: delay wb from exu for one clock cycle to meet timing * CtrlBlock: fix pipeline bug between decode and rename Co-authored-by: NYinan Xu <xuyinan1997@gmail.com>
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- 28 2月, 2021 3 次提交
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由 ljw 提交于
* Ftq: use reg instead 4r_sram * Ftq: use delayed value form exu output
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由 ljw 提交于
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由 William Wang 提交于
* WaitTable: add waittable framework * WaitTable: get replay info from RedirectGenerator * StoreQueue: maintain issuePtr for load rs * RS: add loadWait to rs (only for load Unit's rs) * WaitTable: fix update logic * StoreQueue: fix issuePtr update logic * chore: set loadWaitBit in ibuffer * StoreQueue: fix issuePtrExt update logic Former logic does not work well with mmio logic We may also make sure that issuePtrExt is not before cmtPtrExt * WaitTable: write with priority * StoreQueue: fix issuePtrExt update logic for mmio * chore: fix typos * CSR: add slvpredctrl * slvpredctrl will control load violation predict micro architecture * WaitTable: use xor folded pc to index waittable Co-authored-by: NZhangZifei <1773908404@qq.com>
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- 26 2月, 2021 1 次提交
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由 ljw 提交于
* Backend: fix some bugs related to exu write * Roq: revert to perv verision * Fix fp write back bugs
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- 24 2月, 2021 1 次提交
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由 ljw 提交于
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- 23 2月, 2021 1 次提交
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由 Yinan Xu 提交于
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- 09 2月, 2021 1 次提交
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由 wangkaifan 提交于
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- 04 2月, 2021 1 次提交
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由 zoujr 提交于
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- 02 2月, 2021 2 次提交
- 01 2月, 2021 3 次提交
- 31 1月, 2021 1 次提交
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由 LinJiawei 提交于
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- 30 1月, 2021 1 次提交
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由 Yinan Xu 提交于
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- 29 1月, 2021 1 次提交
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由 LinJiawei 提交于
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- 28 1月, 2021 2 次提交
- 27 1月, 2021 3 次提交
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由 wangkaifan 提交于
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由 wangkaifan 提交于
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由 William Wang 提交于
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- 26 1月, 2021 2 次提交
- 25 1月, 2021 3 次提交
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由 LinJiawei 提交于
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由 wangkaifan 提交于
* should be compatible with single core difftest framework
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由 Yinan Xu 提交于
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- 24 1月, 2021 2 次提交
- 22 1月, 2021 4 次提交