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前往新版Gitcode,体验更适合开发者的 AI 搜索 >>
提交
7aa94463
编写于
1月 25, 2021
作者:
L
LinJiawei
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
fix backend bugs
上级
fe1ab9c6
变更
5
隐藏空白更改
内联
并排
Showing
5 changed file
with
29 addition
and
11 deletion
+29
-11
src/main/scala/xiangshan/backend/CtrlBlock.scala
src/main/scala/xiangshan/backend/CtrlBlock.scala
+4
-2
src/main/scala/xiangshan/backend/exu/Exu.scala
src/main/scala/xiangshan/backend/exu/Exu.scala
+1
-1
src/main/scala/xiangshan/backend/ftq/Ftq.scala
src/main/scala/xiangshan/backend/ftq/Ftq.scala
+7
-4
src/main/scala/xiangshan/backend/fu/Jump.scala
src/main/scala/xiangshan/backend/fu/Jump.scala
+3
-3
src/main/scala/xiangshan/backend/issue/ReservationStationNew.scala
...scala/xiangshan/backend/issue/ReservationStationNew.scala
+14
-1
未找到文件。
src/main/scala/xiangshan/backend/CtrlBlock.scala
浏览文件 @
7aa94463
...
...
@@ -121,7 +121,7 @@ class RedirectGenerator extends XSModule with HasCircularQueuePtrHelper {
val
s2_redirect_valid_reg
=
RegNext
(
s1_redirect_valid_reg
,
init
=
false
.
B
)
val
ftqRead
=
io
.
stage2FtqRead
.
entry
val
pc
=
GetPcByFtq
(
ftqRead
.
ftqPC
,
s2_redirect_bits_reg
.
ftqOffset
)
val
pc
=
GetPcByFtq
(
ftqRead
.
ftqPC
,
s2_redirect_bits_reg
.
ftqOffset
,
ftqRead
.
hasLastPrev
)
val
brTarget
=
pc
+
SignExt
(
ImmUnion
.
B
.
toImm32
(
s2_imm12_reg
),
XLEN
)
val
snpc
=
pc
+
Mux
(
s2_pd
.
isRVC
,
2.
U
,
4.
U
)
val
isReplay
=
RedirectLevel
.
flushItself
(
s2_redirect_bits_reg
.
level
)
...
...
@@ -216,7 +216,9 @@ class CtrlBlock extends XSModule with HasCircularQueuePtrHelper {
val
ftqOffsetReg
=
Reg
(
UInt
(
log2Up
(
PredictWidth
).
W
))
ftqOffsetReg
:=
jumpInst
.
cf
.
ftqOffset
ftq
.
io
.
ftqRead
(
0
).
ptr
:=
jumpInst
.
cf
.
ftqPtr
// jump
io
.
toIntBlock
.
jumpPc
:=
GetPcByFtq
(
ftq
.
io
.
ftqRead
(
0
).
entry
.
ftqPC
,
ftqOffsetReg
)
io
.
toIntBlock
.
jumpPc
:=
GetPcByFtq
(
ftq
.
io
.
ftqRead
(
0
).
entry
.
ftqPC
,
ftqOffsetReg
,
ftq
.
io
.
ftqRead
(
0
).
entry
.
hasLastPrev
)
io
.
toIntBlock
.
jalr_target
:=
ftq
.
io
.
ftqRead
(
0
).
entry
.
target
// pipeline between decode and dispatch
...
...
src/main/scala/xiangshan/backend/exu/Exu.scala
浏览文件 @
7aa94463
...
...
@@ -106,7 +106,7 @@ abstract class Exu(val config: ExuConfig) extends XSModule {
if
(
fuCfg
.
srcCnt
>
0
)
{
fu
.
io
.
in
.
bits
.
src
(
0
)
:=
src1
}
if
(
fuCfg
.
srcCnt
>
1
)
{
if
(
fuCfg
.
srcCnt
>
1
||
fuCfg
==
jmpCfg
)
{
// jump is special for jalr target
fu
.
io
.
in
.
bits
.
src
(
1
)
:=
src2
}
if
(
fuCfg
.
srcCnt
>
2
)
{
...
...
src/main/scala/xiangshan/backend/ftq/Ftq.scala
浏览文件 @
7aa94463
...
...
@@ -17,13 +17,16 @@ object FtqPtr extends HasXSParameter {
}
object
GetPcByFtq
extends
HasXSParameter
{
def
apply
(
ftqPC
:
UInt
,
ftqOffset
:
UInt
)
=
{
def
apply
(
ftqPC
:
UInt
,
ftqOffset
:
UInt
,
hasLastPrev
:
Bool
)
=
{
assert
(
ftqPC
.
getWidth
==
VAddrBits
)
assert
(
ftqOffset
.
getWidth
==
log2Up
(
PredictWidth
))
val
idxBits
=
ftqPC
.
head
(
VAddrBits
-
ftqOffset
.
getWidth
-
instOffsetBits
)
val
selLastPacket
=
hasLastPrev
&&
(
ftqOffset
===
0.
U
)
val
packetIdx
=
Mux
(
selLastPacket
,
idxBits
-
1.
U
,
idxBits
)
Cat
(
ftqPC
.
head
(
VAddrBits
-
ftqOffset
.
getWidth
-
instOffsetBits
)
,
// packet pc
ftqOffset
,
// offset
0.
U
(
instOffsetBits
.
W
)
// 0s
packetIdx
,
// packet pc
Mux
(
selLastPacket
,
Fill
(
ftqOffset
.
getWidth
,
1.
U
(
1.
W
)),
ftqOffset
),
0.
U
(
instOffsetBits
.
W
)
)
}
}
...
...
src/main/scala/xiangshan/backend/fu/Jump.scala
浏览文件 @
7aa94463
...
...
@@ -16,14 +16,14 @@ trait HasRedirectOut { this: RawModule =>
class
Jump
extends
FunctionUnit
with
HasRedirectOut
{
val
(
src1
,
immMin
,
func
,
uop
)
=
(
val
(
src1
,
jalr_target
,
pc
,
immMin
,
func
,
uop
)
=
(
io
.
in
.
bits
.
src
(
0
),
io
.
in
.
bits
.
src
(
1
)(
VAddrBits
-
1
,
0
),
io
.
in
.
bits
.
uop
.
cf
.
pc
,
io
.
in
.
bits
.
uop
.
ctrl
.
imm
,
io
.
in
.
bits
.
uop
.
ctrl
.
fuOpType
,
io
.
in
.
bits
.
uop
)
val
pc
=
src1
(
VAddrBits
-
1
,
0
)
val
jalr_target
=
io
.
in
.
bits
.
src
(
1
)(
VAddrBits
-
1
,
0
)
val
isJalr
=
JumpOpType
.
jumpOpisJalr
(
func
)
val
isAuipc
=
JumpOpType
.
jumpOpisAuipc
(
func
)
...
...
src/main/scala/xiangshan/backend/issue/ReservationStationNew.scala
浏览文件 @
7aa94463
...
...
@@ -361,6 +361,8 @@ class ReservationStationData
// Data
// ------------------------
val
data
=
List
.
tabulate
(
srcNum
)(
_
=>
Module
(
new
SyncDataModuleTemplate
(
UInt
((
XLEN
+
1
).
W
),
iqSize
,
numRead
=
iqSize
+
1
,
numWrite
=
iqSize
)))
val
pcMem
=
if
(
exuCfg
==
Exu
.
jumpExeUnitCfg
)
Some
(
Module
(
new
SyncDataModuleTemplate
(
UInt
(
VAddrBits
.
W
),
iqSize
,
numRead
=
1
,
numWrite
=
1
)))
else
None
data
.
foreach
(
_
.
io
<>
DontCare
)
data
.
foreach
(
_
.
io
.
wen
.
foreach
(
_
:=
false
.
B
))
...
...
@@ -423,6 +425,12 @@ class ReservationStationData
p
"${enqUop.src3State}|${enqUop.ctrl.src3Type} pc:0x${Hexadecimal(enqUop.cf.pc)} roqIdx:${enqUop.roqIdx}\n"
)
}
if
(
pcMem
.
nonEmpty
){
pcMem
.
get
.
io
.
wen
(
0
)
:=
enqEnReg
pcMem
.
get
.
io
.
waddr
(
0
)
:=
enqPtrReg
pcMem
.
get
.
io
.
wdata
(
0
)
:=
io
.
jumpPc
}
when
(
enqEnReg
)
{
exuCfg
match
{
case
Exu
.
jumpExeUnitCfg
=>
...
...
@@ -505,7 +513,12 @@ class ReservationStationData
exuInput
:=
DontCare
exuInput
.
uop
:=
uop
(
deq
)
exuInput
.
uop
.
cf
.
exceptionVec
:=
0.
U
.
asTypeOf
(
ExceptionVec
())
val
regValues
=
List
.
tabulate
(
srcNum
)(
i
=>
dataRead
(
Mux
(
sel
.
valid
,
sel
.
bits
,
deq
),
i
))
val
deqAddr
=
Mux
(
sel
.
valid
,
sel
.
bits
,
deq
)
if
(
pcMem
.
nonEmpty
){
pcMem
.
get
.
io
.
raddr
(
0
)
:=
deqAddr
exuInput
.
uop
.
cf
.
pc
:=
pcMem
.
get
.
io
.
rdata
(
0
)
}
val
regValues
=
List
.
tabulate
(
srcNum
)(
i
=>
dataRead
(
deqAddr
,
i
))
XSDebug
(
io
.
deq
.
fire
(),
p
"[regValues] "
+
List
.
tabulate
(
srcNum
)(
idx
=>
p
"reg$idx: ${Hexadecimal(regValues(idx))}"
).
reduce
((
p1
,
p2
)
=>
p1
+
" "
+
p2
)
+
"\n"
)
exuInput
.
src1
:=
regValues
(
0
)
if
(
srcNum
>
1
)
exuInput
.
src2
:=
regValues
(
1
)
...
...
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