difftest: support dual-core difftest signal in-core

* should be compatible with single core difftest framework

src/main/scala/system/SoC.scala

@@ -8,7 +8,7 @@ import freechips.rocketchip.diplomacy.{AddressSet, LazyModule, LazyModuleImp}
 import freechips.rocketchip.tilelink.{BankBinder, TLBuffer, TLBundleParameters, TLCacheCork, TLClientNode, TLFilter, TLFuzzer, TLIdentityNode, TLToAXI4, TLWidthWidget, TLXbar}
 import utils.{DebugIdentityNode, DataDontCareNode}
 import utils.XSInfo
-import xiangshan.{HasXSParameter, XSCore, HasXSLog}
+import xiangshan.{HasXSParameter, XSCore, HasXSLog, DifftestBundle}
 import sifive.blocks.inclusivecache.{CacheParameters, InclusiveCache, InclusiveCacheMicroParameters}
 import freechips.rocketchip.diplomacy.{AddressSet, LazyModule, LazyModuleImp}
 import freechips.rocketchip.devices.tilelink.{DevNullParams, TLError}
@@ -162,7 +162,9 @@ class XSSoc()(implicit p: Parameters) extends LazyModule with HasSoCParameter {
       // val meip = Input(Vec(NumCores, Bool()))
       val ila = if(env.FPGAPlatform && EnableILA) Some(Output(new ILABundle)) else None
     })
-
+    val difftestIO0 = IO(new DifftestBundle())
+    val difftestIO1 = IO(new DifftestBundle())
+    val difftestIO = Seq(difftestIO0, difftestIO1)
     plic.module.io.extra.get.intrVec <> RegNext(RegNext(Cat(io.extIntrs)))
 
     for (i <- 0 until NumCores) {
@@ -172,6 +174,12 @@ class XSSoc()(implicit p: Parameters) extends LazyModule with HasSoCParameter {
       xs_core(i).module.io.externalInterrupt.meip := plic.module.io.extra.get.meip(i)
       xs_core(i).module.io.l2ToPrefetcher <> l2cache(i).module.io
     }
+    difftestIO0 <> DontCare
+    difftestIO1 <> DontCare
+    if (env.DualCoreDifftest) {
+      difftestIO0 <> xs_core(0).module.difftestIO
+      difftestIO1 <> xs_core(1).module.difftestIO
+    }
     // do not let dma AXI signals optimized out
     chisel3.dontTouch(dma.out.head._1)
     chisel3.dontTouch(extDev.out.head._1)

src/main/scala/xiangshan/Bundle.scala

@@ -399,3 +399,55 @@ class SfenceBundle extends XSBundle {
     p"valid:0x${Hexadecimal(valid)} rs1:${bits.rs1} rs2:${bits.rs2} addr:${Hexadecimal(bits.addr)}"
   }
 }
+
+class DifftestBundle extends XSBundle {
+  val fromSbuffer = new Bundle() {
+    val sbufferResp = Output(Bool())
+    val sbufferAddr = Output(UInt(64.W))
+    val sbufferData = Output(Vec(64, UInt(8.W)))
+    val sbufferMask = Output(UInt(64.W))
+  }
+  val fromSQ = new Bundle() {
+    val storeCommit = Output(UInt(2.W))
+    val storeAddr   = Output(Vec(2, UInt(64.W)))
+    val storeData   = Output(Vec(2, UInt(64.W)))
+    val storeMask   = Output(Vec(2, UInt(8.W)))
+  }
+  val fromXSCore = new Bundle() {
+    val r = Output(Vec(64, UInt(XLEN.W)))
+  }
+  val fromCSR = new Bundle() {
+    val intrNO = Output(UInt(64.W))
+    val cause = Output(UInt(64.W))
+    val priviledgeMode = Output(UInt(2.W))
+    val mstatus = Output(UInt(64.W))
+    val sstatus = Output(UInt(64.W))
+    val mepc = Output(UInt(64.W))
+    val sepc = Output(UInt(64.W))
+    val mtval = Output(UInt(64.W))
+    val stval = Output(UInt(64.W))
+    val mtvec = Output(UInt(64.W))
+    val stvec = Output(UInt(64.W))
+    val mcause = Output(UInt(64.W))
+    val scause = Output(UInt(64.W))
+    val satp = Output(UInt(64.W))
+    val mip = Output(UInt(64.W))
+    val mie = Output(UInt(64.W))
+    val mscratch = Output(UInt(64.W))
+    val sscratch = Output(UInt(64.W))
+    val mideleg = Output(UInt(64.W))
+    val medeleg = Output(UInt(64.W))
+  }
+  val fromRoq = new Bundle() {
+    val commit = Output(UInt(32.W))
+    val thisPC = Output(UInt(XLEN.W))
+    val thisINST = Output(UInt(32.W))
+    val skip = Output(UInt(32.W))
+    val wen = Output(UInt(32.W))
+    val wdata = Output(Vec(CommitWidth, UInt(XLEN.W))) // set difftest width to 6
+    val wdst = Output(Vec(CommitWidth, UInt(32.W))) // set difftest width to 6
+    val wpc = Output(Vec(CommitWidth, UInt(XLEN.W))) // set difftest width to 6
+    val isRVC = Output(UInt(32.W))
+    val scFailed = Output(Bool())
+  }
+}
\ No newline at end of file

src/main/scala/xiangshan/XSCore.scala

@@ -22,6 +22,14 @@ import freechips.rocketchip.tile.HasFPUParameters
 import sifive.blocks.inclusivecache.PrefetcherIO
 import utils._
 
+object hartIdCore extends (() => Int) {
+  var x = 0
+  def apply(): Int = {
+    x = x + 1
+    x-1
+  }
+}
+
 case class XSCoreParameters
 (
   XLEN: Int = 64,
@@ -350,6 +358,8 @@ class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer)
     val externalInterrupt = new ExternalInterruptIO
     val l2ToPrefetcher = Flipped(new PrefetcherIO(PAddrBits))
   })
+  val difftestIO = IO(new DifftestBundle())
+  difftestIO <> DontCare
 
   println(s"FPGAPlatform:${env.FPGAPlatform} EnableDebug:${env.EnableDebug}")
   AddressSpace.printMemmap()
@@ -482,4 +492,18 @@ class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer)
     ExcitingUtils.addSource(debugArchReg, "difftestRegs", ExcitingUtils.Debug)
   }
 
+  if (env.DualCoreDifftest) {
+    val id = hartIdCore()
+    difftestIO.fromSbuffer <> memBlock.difftestIO.fromSbuffer
+    difftestIO.fromSQ <> memBlock.difftestIO.fromSQ
+    difftestIO.fromCSR <> integerBlock.difftestIO.fromCSR
+    difftestIO.fromRoq <> ctrlBlock.difftestIO.fromRoq
+
+    val debugIntReg, debugFpReg = WireInit(VecInit(Seq.fill(32)(0.U(XLEN.W))))
+    ExcitingUtils.addSink(debugIntReg, s"DEBUG_INT_ARCH_REG$id", ExcitingUtils.Debug)
+    ExcitingUtils.addSink(debugFpReg, s"DEBUG_FP_ARCH_REG$id", ExcitingUtils.Debug)
+    val debugArchReg = WireInit(VecInit(debugIntReg ++ debugFpReg))
+    difftestIO.fromXSCore.r := debugArchReg
+  }
+
 }

src/main/scala/xiangshan/backend/CtrlBlock.scala

@@ -57,6 +57,22 @@ class CtrlBlock extends XSModule with HasCircularQueuePtrHelper {
     }
   })
 
+  val difftestIO = IO(new Bundle() {
+    val fromRoq = new Bundle() {
+      val commit = Output(UInt(32.W))
+      val thisPC = Output(UInt(XLEN.W))
+      val thisINST = Output(UInt(32.W))
+      val skip = Output(UInt(32.W))
+      val wen = Output(UInt(32.W))
+      val wdata = Output(Vec(CommitWidth, UInt(XLEN.W))) // set difftest width to 6
+      val wdst = Output(Vec(CommitWidth, UInt(32.W))) // set difftest width to 6
+      val wpc = Output(Vec(CommitWidth, UInt(XLEN.W))) // set difftest width to 6
+      val isRVC = Output(UInt(32.W))
+      val scFailed = Output(Bool())
+    }
+  })
+  difftestIO <> DontCare
+
   val decode = Module(new DecodeStage)
   val brq = Module(new Brq)
   val rename = Module(new Rename)
@@ -145,6 +161,10 @@ class CtrlBlock extends XSModule with HasCircularQueuePtrHelper {
   }
   roq.io.exeWbResults.last := brq.io.out
 
+  if (env.DualCoreDifftest) {
+    difftestIO.fromRoq <> roq.difftestIO
+  }
+
   io.toIntBlock.redirect.valid := redirectValid
   io.toIntBlock.redirect.bits := redirect
   io.toFpBlock.redirect.valid := redirectValid

src/main/scala/xiangshan/backend/IntegerBlock.scala

@@ -92,6 +92,31 @@ class IntegerBlock
       val sbuffer = new FenceToSbuffer      // to mem
     }
   })
+  val difftestIO = IO(new Bundle() {
+    val fromCSR = new Bundle() {
+      val intrNO = Output(UInt(64.W))
+      val cause = Output(UInt(64.W))
+      val priviledgeMode = Output(UInt(2.W))
+      val mstatus = Output(UInt(64.W))
+      val sstatus = Output(UInt(64.W))
+      val mepc = Output(UInt(64.W))
+      val sepc = Output(UInt(64.W))
+      val mtval = Output(UInt(64.W))
+      val stval = Output(UInt(64.W))
+      val mtvec = Output(UInt(64.W))
+      val stvec = Output(UInt(64.W))
+      val mcause = Output(UInt(64.W))
+      val scause = Output(UInt(64.W))
+      val satp = Output(UInt(64.W))
+      val mip = Output(UInt(64.W))
+      val mie = Output(UInt(64.W))
+      val mscratch = Output(UInt(64.W))
+      val sscratch = Output(UInt(64.W))
+      val mideleg = Output(UInt(64.W))
+      val medeleg = Output(UInt(64.W))
+    }
+  })
+  difftestIO <> DontCare
 
   val redirect = io.fromCtrlBlock.redirect
 
@@ -216,6 +241,9 @@ class IntegerBlock
 
   jmpExeUnit.csrio <> io.csrio
   jmpExeUnit.fenceio <> io.fenceio
+  if (env.DualCoreDifftest) {
+    jmpExeUnit.difftestIO.fromCSR <> difftestIO.fromCSR
+  }
 
   // read int rf from ctrl block
   intRf.io.readPorts.zipWithIndex.map{ case(r, i) => r.addr := io.fromCtrlBlock.readRf(i) }

src/main/scala/xiangshan/backend/MemBlock.scala

@@ -83,6 +83,21 @@ class MemBlockImp
 
     val toDCachePrefetch = DecoupledIO(new MissReq)
   })
+  val difftestIO = IO(new Bundle() {
+    val fromSbuffer = new Bundle() {
+      val sbufferResp = Output(Bool())
+      val sbufferAddr = Output(UInt(64.W))
+      val sbufferData = Output(Vec(64, UInt(8.W)))
+      val sbufferMask = Output(UInt(64.W))
+    }
+    val fromSQ = new Bundle() {
+      val storeCommit = Output(UInt(2.W))
+      val storeAddr   = Output(Vec(2, UInt(64.W)))
+      val storeData   = Output(Vec(2, UInt(64.W)))
+      val storeMask   = Output(Vec(2, UInt(8.W)))
+    }
+  })
+  difftestIO <> DontCare
 
   val dcache = outer.dcache.module
   val uncache = outer.uncache.module
@@ -195,6 +210,10 @@ class MemBlockImp
   io.ptw         <> dtlb.io.ptw
   dtlb.io.sfence <> io.sfence
   dtlb.io.csr    <> io.tlbCsr
+  if (env.DualCoreDifftest) {
+    difftestIO.fromSbuffer <> sbuffer.difftestIO
+    difftestIO.fromSQ <> lsq.difftestIO.fromSQ
+  }
 
   // LoadUnit
   for (i <- 0 until exuParameters.LduCnt) {

src/main/scala/xiangshan/backend/exu/JumpExeUnit.scala

@@ -30,6 +30,31 @@ class JumpExeUnit extends Exu(jumpExeUnitCfg)
     val fencei = Output(Bool())
     val sbuffer = new FenceToSbuffer
   })
+  val difftestIO = IO(new Bundle() {
+    val fromCSR = new Bundle() {
+      val intrNO = Output(UInt(64.W))
+      val cause = Output(UInt(64.W))
+      val priviledgeMode = Output(UInt(2.W))
+      val mstatus = Output(UInt(64.W))
+      val sstatus = Output(UInt(64.W))
+      val mepc = Output(UInt(64.W))
+      val sepc = Output(UInt(64.W))
+      val mtval = Output(UInt(64.W))
+      val stval = Output(UInt(64.W))
+      val mtvec = Output(UInt(64.W))
+      val stvec = Output(UInt(64.W))
+      val mcause = Output(UInt(64.W))
+      val scause = Output(UInt(64.W))
+      val satp = Output(UInt(64.W))
+      val mip = Output(UInt(64.W))
+      val mie = Output(UInt(64.W))
+      val mscratch = Output(UInt(64.W))
+      val sscratch = Output(UInt(64.W))
+      val mideleg = Output(UInt(64.W))
+      val medeleg = Output(UInt(64.W))
+    }
+  })
+  difftestIO <> DontCare
 
   val jmp = supportedFunctionUnits.collectFirst{
     case j: Jump => j
@@ -58,6 +83,10 @@ class JumpExeUnit extends Exu(jumpExeUnitCfg)
   csr.csrio.externalInterrupt <> csrio.externalInterrupt
   csr.csrio.tlb <> csrio.tlb
 
+  if (env.DualCoreDifftest) {
+    difftestIO.fromCSR <> csr.difftestIO
+  }
+
   fenceio.sfence <> fence.sfence
   fenceio.fencei <> fence.fencei
   fenceio.sbuffer <> fence.toSbuffer

src/main/scala/xiangshan/backend/fu/CSR.scala

@@ -145,6 +145,29 @@ class CSR extends FunctionUnit with HasCSRConst
     // TLB
     val tlb = Output(new TlbCsrBundle)
   })
+  val difftestIO = IO(new Bundle() {
+    val intrNO = Output(UInt(64.W))
+    val cause = Output(UInt(64.W))
+    val priviledgeMode = Output(UInt(2.W))
+    val mstatus = Output(UInt(64.W))
+    val sstatus = Output(UInt(64.W))
+    val mepc = Output(UInt(64.W))
+    val sepc = Output(UInt(64.W))
+    val mtval = Output(UInt(64.W))
+    val stval = Output(UInt(64.W))
+    val mtvec = Output(UInt(64.W))
+    val stvec = Output(UInt(64.W))
+    val mcause = Output(UInt(64.W))
+    val scause = Output(UInt(64.W))
+    val satp = Output(UInt(64.W))
+    val mip = Output(UInt(64.W))
+    val mie = Output(UInt(64.W))
+    val mscratch = Output(UInt(64.W))
+    val sscratch = Output(UInt(64.W))
+    val mideleg = Output(UInt(64.W))
+    val medeleg = Output(UInt(64.W))
+  })
+  difftestIO <> DontCare
 
   val cfIn = io.in.bits.uop.cf
   val cfOut = Wire(new CtrlFlow)
@@ -852,6 +875,8 @@ class CSR extends FunctionUnit with HasCSRConst
   }
   def readWithScala(addr: Int): UInt = mapping(addr)._1
 
+  val difftestIntrNO = Mux(raiseIntr, causeNO, 0.U)
+  
   if (!env.FPGAPlatform) {
 
     // display all perfcnt when nooptrap is executed
@@ -862,7 +887,6 @@ class CSR extends FunctionUnit with HasCSRConst
       }
     }
 
-    val difftestIntrNO = Mux(raiseIntr, causeNO, 0.U)
     ExcitingUtils.addSource(difftestIntrNO, "difftestIntrNOfromCSR")
     ExcitingUtils.addSource(causeNO, "difftestCausefromCSR")
     ExcitingUtils.addSource(priviledgeMode, "difftestMode", Debug)
@@ -884,4 +908,27 @@ class CSR extends FunctionUnit with HasCSRConst
     ExcitingUtils.addSource(mideleg, "difftestMideleg", Debug)
     ExcitingUtils.addSource(medeleg, "difftestMedeleg", Debug)
   }
+
+  if (env.DualCoreDifftest) {
+    difftestIO.intrNO := RegNext(difftestIntrNO)
+    difftestIO.cause := RegNext(causeNO)
+    difftestIO.priviledgeMode := priviledgeMode
+    difftestIO.mstatus := mstatus
+    difftestIO.sstatus := mstatus & sstatusRmask
+    difftestIO.mepc := mepc
+    difftestIO.sepc := sepc
+    difftestIO.mtval:= mtval
+    difftestIO.stval:= stval
+    difftestIO.mtvec := mtvec
+    difftestIO.stvec := stvec
+    difftestIO.mcause := mcause
+    difftestIO.scause := scause
+    difftestIO.satp := satp
+    difftestIO.mip := mipReg
+    difftestIO.mie := mie
+    difftestIO.mscratch := mscratch
+    difftestIO.sscratch := sscratch
+    difftestIO.mideleg := mideleg
+    difftestIO.medeleg := medeleg
+  }
 }

src/main/scala/xiangshan/backend/regfile/Regfile.scala

@@ -4,6 +4,22 @@ import chisel3._
 import chisel3.util._
 import xiangshan._
 
+object hartIdRFInt extends (() => Int) {
+  var x = 0
+  def apply(): Int = {
+    x = x + 1
+    x-1
+  }
+}
+
+object hartIdRFFp extends (() => Int) {
+  var x = 0
+  def apply(): Int = {
+    x = x + 1
+    x-1
+  }
+}
+
 class RfReadPort(len: Int) extends XSBundle {
   val addr = Input(UInt(PhyRegIdxWidth.W))
   val data = Output(UInt(len.W))
@@ -65,6 +81,29 @@ class Regfile
         ExcitingUtils.Debug
       )
     }
+
+    if (env.DualCoreDifftest) {
+      val id = if (hasZero) hartIdRFInt() else hartIdRFFp()
+      val debugArchRat = WireInit(VecInit(Seq.fill(32)(0.U(PhyRegIdxWidth.W))))
+      ExcitingUtils.addSink(
+        debugArchRat,
+        if(hasZero) s"DEBUG_INI_ARCH_RAT$id" else s"DEBUG_FP_ARCH_RAT$id",
+        ExcitingUtils.Debug
+      )
+
+      val debugArchReg = WireInit(VecInit(debugArchRat.zipWithIndex.map(
+        x => if(hasZero){
+          if(x._2 == 0) 0.U else mem(x._1)
+        } else {
+          ieee(mem(x._1))
+        }
+      )))
+      ExcitingUtils.addSource(
+        debugArchReg,
+        if(hasZero) s"DEBUG_INT_ARCH_REG$id" else s"DEBUG_FP_ARCH_REG$id",
+        ExcitingUtils.Debug
+      )
+    }
   } else {
 
     val regfile = Module(new regfile_160x64_10w16r_sim)

src/main/scala/xiangshan/backend/rename/RenameTable.scala

@@ -15,6 +15,22 @@ class RatWritePort extends XSBundle {
   val wdata = Input(UInt(PhyRegIdxWidth.W))
 }
 
+object hartIdRTInt extends (() => Int) {
+  var x = 0
+  def apply(): Int = {
+    x = x + 1
+    x-1
+  }
+}
+
+object hartIdRTFp extends (() => Int) {
+  var x = 0
+  def apply(): Int = {
+    x = x + 1
+    x-1
+  }
+}
+
 class RenameTable(float: Boolean) extends XSModule {
   val io = IO(new Bundle() {
     val redirect = Flipped(ValidIO(new Redirect))
@@ -65,4 +81,13 @@ class RenameTable(float: Boolean) extends XSModule {
       ExcitingUtils.Debug
     )
   }
+
+  if (env.DualCoreDifftest) {
+    val id = if (float) hartIdRTFp() else hartIdRTInt()
+    ExcitingUtils.addSource(
+      arch_table,
+      if(float) s"DEBUG_FP_ARCH_RAT$id" else s"DEBUG_INI_ARCH_RAT$id",
+      ExcitingUtils.Debug
+    )
+  }
 }

src/main/scala/xiangshan/backend/roq/Roq.scala

@@ -209,6 +209,20 @@ class Roq(numWbPorts: Int) extends XSModule with HasCircularQueuePtrHelper {
     val csr = new RoqCSRIO
   })
 
+  val difftestIO = IO(new Bundle() {
+    val commit = Output(UInt(32.W))
+    val thisPC = Output(UInt(XLEN.W))
+    val thisINST = Output(UInt(32.W))
+    val skip = Output(UInt(32.W))
+    val wen = Output(UInt(32.W))
+    val wdata = Output(Vec(CommitWidth, UInt(XLEN.W))) // set difftest width to 6
+    val wdst = Output(Vec(CommitWidth, UInt(32.W))) // set difftest width to 6
+    val wpc = Output(Vec(CommitWidth, UInt(XLEN.W))) // set difftest width to 6
+    val isRVC = Output(UInt(32.W))
+    val scFailed = Output(Bool())
+  })
+  difftestIO <> DontCare
+
   // instvalid field
   // val valid = RegInit(VecInit(List.fill(RoqSize)(false.B)))
   val valid = Mem(RoqSize, Bool())
@@ -718,55 +732,55 @@ class Roq(numWbPorts: Int) extends XSModule with HasCircularQueuePtrHelper {
   instrCnt := instrCnt + retireCounter
   io.csr.perfinfo.retiredInstr := RegNext(retireCounter)
 
-  if(!env.FPGAPlatform) {
-
-    //difftest signals
-    val firstValidCommit = (deqPtr + PriorityMux(io.commits.valid, VecInit(List.tabulate(CommitWidth)(_.U)))).value
-
-    val skip = Wire(Vec(CommitWidth, Bool()))
-    val wen = Wire(Vec(CommitWidth, Bool()))
-    val wdata = Wire(Vec(CommitWidth, UInt(XLEN.W)))
-    val wdst = Wire(Vec(CommitWidth, UInt(32.W)))
-    val diffTestDebugLrScValid = Wire(Vec(CommitWidth, Bool()))
-    val wpc = Wire(Vec(CommitWidth, UInt(XLEN.W)))
-    val trapVec = Wire(Vec(CommitWidth, Bool()))
-    val isRVC = Wire(Vec(CommitWidth, Bool()))
-    for(i <- 0 until CommitWidth){
-      // io.commits(i).valid
-      val idx = deqPtrVec(i).value
-      val uop = debug_microOp(idx)
-      val DifftestSkipSC = false
-      if(!DifftestSkipSC){
-        skip(i) := (debug_exuDebug(idx).isMMIO || debug_exuDebug(idx).isPerfCnt) && io.commits.valid(i)
-      }else{
-        skip(i) := (
-            debug_exuDebug(idx).isMMIO ||
-            debug_exuDebug(idx).isPerfCnt ||
-            uop.ctrl.fuType === FuType.mou && uop.ctrl.fuOpType === LSUOpType.sc_d ||
-            uop.ctrl.fuType === FuType.mou && uop.ctrl.fuOpType === LSUOpType.sc_w
-          ) && io.commits.valid(i)
-      }
-      wen(i) := io.commits.valid(i) && uop.ctrl.rfWen && uop.ctrl.ldest =/= 0.U
-      wdata(i) := debug_exuData(idx)
-      wdst(i) := uop.ctrl.ldest
-      diffTestDebugLrScValid(i) := uop.diffTestDebugLrScValid
-      wpc(i) := SignExt(uop.cf.pc, XLEN)
-      trapVec(i) := io.commits.valid(i) && (state===s_idle) && uop.ctrl.isXSTrap
-      isRVC(i) := uop.cf.brUpdate.pd.isRVC
+  //difftest signals
+  val firstValidCommit = (deqPtr + PriorityMux(io.commits.valid, VecInit(List.tabulate(CommitWidth)(_.U)))).value
+
+  val skip = Wire(Vec(CommitWidth, Bool()))
+  val wen = Wire(Vec(CommitWidth, Bool()))
+  val wdata = Wire(Vec(CommitWidth, UInt(XLEN.W)))
+  val wdst = Wire(Vec(CommitWidth, UInt(32.W)))
+  val diffTestDebugLrScValid = Wire(Vec(CommitWidth, Bool()))
+  val wpc = Wire(Vec(CommitWidth, UInt(XLEN.W)))
+  val trapVec = Wire(Vec(CommitWidth, Bool()))
+  val isRVC = Wire(Vec(CommitWidth, Bool()))
+  for(i <- 0 until CommitWidth) {
+    // io.commits(i).valid
+    val idx = deqPtrVec(i).value
+    val uop = debug_microOp(idx)
+    val DifftestSkipSC = false
+    if(!DifftestSkipSC){
+      skip(i) := (debug_exuDebug(idx).isMMIO || debug_exuDebug(idx).isPerfCnt) && io.commits.valid(i)
+    }else{
+      skip(i) := (
+          debug_exuDebug(idx).isMMIO ||
+          debug_exuDebug(idx).isPerfCnt ||
+          uop.ctrl.fuType === FuType.mou && uop.ctrl.fuOpType === LSUOpType.sc_d ||
+          uop.ctrl.fuType === FuType.mou && uop.ctrl.fuOpType === LSUOpType.sc_w
+        ) && io.commits.valid(i)
     }
+    wen(i) := io.commits.valid(i) && uop.ctrl.rfWen && uop.ctrl.ldest =/= 0.U
+    wdata(i) := debug_exuData(idx)
+    wdst(i) := uop.ctrl.ldest
+    diffTestDebugLrScValid(i) := uop.diffTestDebugLrScValid
+    wpc(i) := SignExt(uop.cf.pc, XLEN)
+    trapVec(i) := io.commits.valid(i) && (state===s_idle) && uop.ctrl.isXSTrap
+    isRVC(i) := uop.cf.brUpdate.pd.isRVC
+  }
+  val retireCounterFix = Mux(io.redirectOut.valid, 1.U, retireCounter)
+  val retirePCFix = SignExt(Mux(io.redirectOut.valid, debug_deqUop.cf.pc, debug_microOp(firstValidCommit).cf.pc), XLEN)
+  val retireInstFix = Mux(io.redirectOut.valid, debug_deqUop.cf.instr, debug_microOp(firstValidCommit).cf.instr)
 
-    val scFailed = !diffTestDebugLrScValid(0) &&
-      debug_deqUop.ctrl.fuType === FuType.mou &&
-      (debug_deqUop.ctrl.fuOpType === LSUOpType.sc_d || debug_deqUop.ctrl.fuOpType === LSUOpType.sc_w)
+  val scFailed = !diffTestDebugLrScValid(0) &&
+    debug_deqUop.ctrl.fuType === FuType.mou &&
+    (debug_deqUop.ctrl.fuOpType === LSUOpType.sc_d || debug_deqUop.ctrl.fuOpType === LSUOpType.sc_w)
+
+  if (!env.FPGAPlatform) {
 
     val difftestIntrNO = WireInit(0.U(XLEN.W))
     val difftestCause = WireInit(0.U(XLEN.W))
     ExcitingUtils.addSink(difftestIntrNO, "difftestIntrNOfromCSR")
     ExcitingUtils.addSink(difftestCause, "difftestCausefromCSR")
     XSDebug(difftestIntrNO =/= 0.U, "difftest intrNO set %x\n", difftestIntrNO)
-    val retireCounterFix = Mux(io.redirectOut.valid, 1.U, retireCounter)
-    val retirePCFix = SignExt(Mux(io.redirectOut.valid, debug_deqUop.cf.pc, debug_microOp(firstValidCommit).cf.pc), XLEN)
-    val retireInstFix = Mux(io.redirectOut.valid, debug_deqUop.cf.instr, debug_microOp(firstValidCommit).cf.instr)
 
     ExcitingUtils.addSource(RegNext(retireCounterFix), "difftestCommit", ExcitingUtils.Debug)
     ExcitingUtils.addSource(RegNext(retirePCFix), "difftestThisPC", ExcitingUtils.Debug)//first valid PC
@@ -795,4 +809,17 @@ class Roq(numWbPorts: Int) extends XSModule with HasCircularQueuePtrHelper {
       ExcitingUtils.addSource(hitTrap, "XSTRAP", ConnectionType.Debug)
     }
   }
+
+  if (env.DualCoreDifftest) {
+    difftestIO.commit := RegNext(retireCounterFix)
+    difftestIO.thisPC := RegNext(retirePCFix)
+    difftestIO.thisINST := RegNext(retireInstFix)
+    difftestIO.skip := RegNext(skip.asUInt)
+    difftestIO.wen := RegNext(wen.asUInt)
+    difftestIO.wdata := RegNext(wdata)
+    difftestIO.wdst := RegNext(wdst)
+    difftestIO.wpc := RegNext(wpc)
+    difftestIO.isRVC := RegNext(isRVC.asUInt)
+    difftestIO.scFailed := RegNext(scFailed)
+  }
 }

src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala

@@ -53,6 +53,15 @@ class LsqWrappper extends XSModule with HasDCacheParameters {
     val exceptionAddr = new ExceptionAddrIO
     val sqempty = Output(Bool())
   })
+  val difftestIO = IO(new Bundle() {
+    val fromSQ = new Bundle() {
+      val storeCommit = Output(UInt(2.W))
+      val storeAddr   = Output(Vec(2, UInt(64.W)))
+      val storeData   = Output(Vec(2, UInt(64.W)))
+      val storeMask   = Output(Vec(2, UInt(8.W)))
+    }
+  })
+  difftestIO <> DontCare
 
   val loadQueue = Module(new LoadQueue)
   val storeQueue = Module(new StoreQueue)
@@ -106,6 +115,10 @@ class LsqWrappper extends XSModule with HasDCacheParameters {
 
   storeQueue.io.sqempty <> io.sqempty
 
+  if (env.DualCoreDifftest) {
+    difftestIO.fromSQ <> storeQueue.difftestIO
+  }
+
   io.exceptionAddr.vaddr := Mux(io.exceptionAddr.isStore, storeQueue.io.exceptionAddr.vaddr, loadQueue.io.exceptionAddr.vaddr)
 
   // naive uncache arbiter

src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala

@@ -46,6 +46,14 @@ class StoreQueue extends XSModule with HasDCacheParameters with HasCircularQueue
     val sqempty = Output(Bool())
   })
 
+  val difftestIO = IO(new Bundle() {
+    val storeCommit = Output(UInt(2.W))
+    val storeAddr   = Output(Vec(2, UInt(64.W)))
+    val storeData   = Output(Vec(2, UInt(64.W)))
+    val storeMask   = Output(Vec(2, UInt(8.W)))
+  })
+  difftestIO <> DontCare
+
   // data modules
   val uop = Reg(Vec(StoreQueueSize, new MicroOp))
   // val data = Reg(Vec(StoreQueueSize, new LsqEntry))
@@ -309,17 +317,23 @@ class StoreQueue extends XSModule with HasDCacheParameters with HasCircularQueue
     assert(io.sbuffer(0).fire())
   }
 
-  if (!env.FPGAPlatform) {
-    val storeCommit = PopCount(io.sbuffer.map(_.fire()))
-    val waddr = VecInit(io.sbuffer.map(req => SignExt(req.bits.addr, 64)))
-    val wdata = VecInit(io.sbuffer.map(req => req.bits.data & MaskExpand(req.bits.mask)))
-    val wmask = VecInit(io.sbuffer.map(_.bits.mask))
+  val storeCommit = PopCount(io.sbuffer.map(_.fire()))
+  val waddr = VecInit(io.sbuffer.map(req => SignExt(req.bits.addr, 64)))
+  val wdata = VecInit(io.sbuffer.map(req => req.bits.data & MaskExpand(req.bits.mask)))
+  val wmask = VecInit(io.sbuffer.map(_.bits.mask))
 
+  if (!env.FPGAPlatform) {
     ExcitingUtils.addSource(RegNext(storeCommit), "difftestStoreCommit", ExcitingUtils.Debug)
     ExcitingUtils.addSource(RegNext(waddr), "difftestStoreAddr", ExcitingUtils.Debug)
     ExcitingUtils.addSource(RegNext(wdata), "difftestStoreData", ExcitingUtils.Debug)
     ExcitingUtils.addSource(RegNext(wmask), "difftestStoreMask", ExcitingUtils.Debug)
   }
+  if (env.DualCoreDifftest) {
+    difftestIO.storeCommit := RegNext(storeCommit)
+    difftestIO.storeAddr   := RegNext(waddr)
+    difftestIO.storeData   := RegNext(wdata)
+    difftestIO.storeMask   := RegNext(wmask)
+  }
 
   // Read vaddr for mem exception
   io.exceptionAddr.vaddr := vaddrModule.io.rdata(0)

src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala

@@ -114,6 +114,13 @@ class NewSbuffer extends XSModule with HasSbufferCst {
       val empty = Output(Bool())
     } // sbuffer flush
   })
+  val difftestIO = IO(new Bundle() {
+    val sbufferResp = Output(Bool())
+    val sbufferAddr = Output(UInt(64.W))
+    val sbufferData = Output(Vec(64, UInt(8.W)))
+    val sbufferMask = Output(UInt(64.W))
+  })
+  difftestIO <> DontCare
 
   val buffer = Mem(StoreBufferSize, new SbufferLine)
   val stateVec = RegInit(VecInit(Seq.fill(StoreBufferSize)(s_invalid)))
@@ -376,6 +383,13 @@ class NewSbuffer extends XSModule with HasSbufferCst {
     XSDebug(p"recv cache resp: id=[$respId]\n")
   }
 
+  if (env.DualCoreDifftest) {
+    difftestIO.sbufferResp := WireInit(io.dcache.resp.fire())
+    difftestIO.sbufferAddr := WireInit(getAddr(tagRead(respId)))
+    difftestIO.sbufferData := WireInit(bufferRead(respId).data.asTypeOf(Vec(CacheLineBytes, UInt(8.W))))
+    difftestIO.sbufferMask := WireInit(bufferRead(respId).mask)
+  }
+
   val needSpace = (io.in(0).fire && !canMerge(0)) +& (io.in(1).fire && !canMerge(1) && !sameTag)
   invalidCount := invalidCount - needSpace + io.dcache.resp.fire()
   validCount := validCount + needSpace - prepareValid

src/test/scala/top/XSSim.scala

@@ -53,6 +53,11 @@ class DiffTestIO extends XSBundle {
   val storeAddr   = Output(Vec(2, UInt(64.W)))
   val storeData   = Output(Vec(2, UInt(64.W)))
   val storeMask   = Output(Vec(2, UInt(8.W)))
+
+  val sbufferResp = Output(Bool())
+  val sbufferAddr = Output(UInt(64.W))
+  val sbufferData = Output(Vec(64, UInt(8.W)))
+  val sbufferMask = Output(UInt(64.W))
 }
 
 class LogCtrlIO extends Bundle {
@@ -112,11 +117,13 @@ class XSSimSoC(axiSim: Boolean)(implicit p: config.Parameters) extends LazyModul
 
   lazy val module = new LazyModuleImp(this) {
     val io = IO(new Bundle {
-      val difftest = new DiffTestIO
+      val difftest  = new DiffTestIO
+      val difftest2 = new DiffTestIO
       val logCtrl = new LogCtrlIO
       val trap = new TrapIO
       val uart = new UARTIO
     })
+    io.difftest2 <> DontCare
 
     dontTouch(io.difftest)
     dontTouch(io.logCtrl)
@@ -129,47 +136,97 @@ class XSSimSoC(axiSim: Boolean)(implicit p: config.Parameters) extends LazyModul
       soc.module.io.extIntrs(i) := false.B
     }
 
-    val difftest = WireInit(0.U.asTypeOf(new DiffTestIO))
+    val difftest = Seq(WireInit(0.U.asTypeOf(new DiffTestIO)), WireInit(0.U.asTypeOf(new DiffTestIO)))
+    
     if (!env.FPGAPlatform) {
-      ExcitingUtils.addSink(difftest.commit, "difftestCommit", Debug)
-      ExcitingUtils.addSink(difftest.thisPC, "difftestThisPC", Debug)
-      ExcitingUtils.addSink(difftest.thisINST, "difftestThisINST", Debug)
-      ExcitingUtils.addSink(difftest.skip, "difftestSkip", Debug)
-      ExcitingUtils.addSink(difftest.isRVC, "difftestIsRVC", Debug)
-      ExcitingUtils.addSink(difftest.wen, "difftestWen", Debug)
-      ExcitingUtils.addSink(difftest.wdata, "difftestWdata", Debug)
-      ExcitingUtils.addSink(difftest.wdst, "difftestWdst", Debug)
-      ExcitingUtils.addSink(difftest.wpc, "difftestWpc", Debug)
-      ExcitingUtils.addSink(difftest.intrNO, "difftestIntrNO", Debug)
-      ExcitingUtils.addSink(difftest.cause, "difftestCause", Debug)
-      ExcitingUtils.addSink(difftest.r, "difftestRegs", Debug)
-      ExcitingUtils.addSink(difftest.priviledgeMode, "difftestMode", Debug)
-      ExcitingUtils.addSink(difftest.mstatus, "difftestMstatus", Debug)
-      ExcitingUtils.addSink(difftest.sstatus, "difftestSstatus", Debug)
-      ExcitingUtils.addSink(difftest.mepc, "difftestMepc", Debug)
-      ExcitingUtils.addSink(difftest.sepc, "difftestSepc", Debug)
-      ExcitingUtils.addSink(difftest.mtval, "difftestMtval", Debug)
-      ExcitingUtils.addSink(difftest.stval, "difftestStval", Debug)
-      ExcitingUtils.addSink(difftest.mtvec, "difftestMtvec", Debug)
-      ExcitingUtils.addSink(difftest.stvec, "difftestStvec", Debug)
-      ExcitingUtils.addSink(difftest.mcause, "difftestMcause", Debug)
-      ExcitingUtils.addSink(difftest.scause, "difftestScause", Debug)
-      ExcitingUtils.addSink(difftest.satp, "difftestSatp", Debug)
-      ExcitingUtils.addSink(difftest.mip, "difftestMip", Debug)
-      ExcitingUtils.addSink(difftest.mie, "difftestMie", Debug)
-      ExcitingUtils.addSink(difftest.mscratch, "difftestMscratch", Debug)
-      ExcitingUtils.addSink(difftest.sscratch, "difftestSscratch", Debug)
-      ExcitingUtils.addSink(difftest.mideleg, "difftestMideleg", Debug)
-      ExcitingUtils.addSink(difftest.medeleg, "difftestMedeleg", Debug)
-      ExcitingUtils.addSink(difftest.scFailed, "difftestScFailed", Debug)
-      ExcitingUtils.addSink(difftest.storeCommit, "difftestStoreCommit", Debug)
-      ExcitingUtils.addSink(difftest.storeAddr, "difftestStoreAddr", Debug)
-      ExcitingUtils.addSink(difftest.storeData, "difftestStoreData", Debug)
-      ExcitingUtils.addSink(difftest.storeMask, "difftestStoreMask", Debug)
+      ExcitingUtils.addSink(difftest(0).commit, "difftestCommit", Debug)
+      ExcitingUtils.addSink(difftest(0).thisPC, "difftestThisPC", Debug)
+      ExcitingUtils.addSink(difftest(0).thisINST, "difftestThisINST", Debug)
+      ExcitingUtils.addSink(difftest(0).skip, "difftestSkip", Debug)
+      ExcitingUtils.addSink(difftest(0).isRVC, "difftestIsRVC", Debug)
+      ExcitingUtils.addSink(difftest(0).wen, "difftestWen", Debug)
+      ExcitingUtils.addSink(difftest(0).wdata, "difftestWdata", Debug)
+      ExcitingUtils.addSink(difftest(0).wdst, "difftestWdst", Debug)
+      ExcitingUtils.addSink(difftest(0).wpc, "difftestWpc", Debug)
+      ExcitingUtils.addSink(difftest(0).intrNO, "difftestIntrNO", Debug)
+      ExcitingUtils.addSink(difftest(0).cause, "difftestCause", Debug)
+      ExcitingUtils.addSink(difftest(0).r, "difftestRegs", Debug)
+      ExcitingUtils.addSink(difftest(0).priviledgeMode, "difftestMode", Debug)
+      ExcitingUtils.addSink(difftest(0).mstatus, "difftestMstatus", Debug)
+      ExcitingUtils.addSink(difftest(0).sstatus, "difftestSstatus", Debug)
+      ExcitingUtils.addSink(difftest(0).mepc, "difftestMepc", Debug)
+      ExcitingUtils.addSink(difftest(0).sepc, "difftestSepc", Debug)
+      ExcitingUtils.addSink(difftest(0).mtval, "difftestMtval", Debug)
+      ExcitingUtils.addSink(difftest(0).stval, "difftestStval", Debug)
+      ExcitingUtils.addSink(difftest(0).mtvec, "difftestMtvec", Debug)
+      ExcitingUtils.addSink(difftest(0).stvec, "difftestStvec", Debug)
+      ExcitingUtils.addSink(difftest(0).mcause, "difftestMcause", Debug)
+      ExcitingUtils.addSink(difftest(0).scause, "difftestScause", Debug)
+      ExcitingUtils.addSink(difftest(0).satp, "difftestSatp", Debug)
+      ExcitingUtils.addSink(difftest(0).mip, "difftestMip", Debug)
+      ExcitingUtils.addSink(difftest(0).mie, "difftestMie", Debug)
+      ExcitingUtils.addSink(difftest(0).mscratch, "difftestMscratch", Debug)
+      ExcitingUtils.addSink(difftest(0).sscratch, "difftestSscratch", Debug)
+      ExcitingUtils.addSink(difftest(0).mideleg, "difftestMideleg", Debug)
+      ExcitingUtils.addSink(difftest(0).medeleg, "difftestMedeleg", Debug)
+      ExcitingUtils.addSink(difftest(0).scFailed, "difftestScFailed", Debug)
+      ExcitingUtils.addSink(difftest(0).storeCommit, "difftestStoreCommit", Debug)
+      ExcitingUtils.addSink(difftest(0).storeAddr, "difftestStoreAddr", Debug)
+      ExcitingUtils.addSink(difftest(0).storeData, "difftestStoreData", Debug)
+      ExcitingUtils.addSink(difftest(0).storeMask, "difftestStoreMask", Debug)
+    }
+
+    if (env.DualCoreDifftest) {
+      for (i <- 0 until NumCores) {
+        difftest(i).commit := soc.module.difftestIO(i).fromRoq.commit
+        difftest(i).thisPC := soc.module.difftestIO(i).fromRoq.thisPC
+        difftest(i).thisINST := soc.module.difftestIO(i).fromRoq.thisINST
+        difftest(i).skip := soc.module.difftestIO(i).fromRoq.skip
+        difftest(i).isRVC := soc.module.difftestIO(i).fromRoq.isRVC
+        difftest(i).wen := soc.module.difftestIO(i).fromRoq.wen
+        difftest(i).wdata := soc.module.difftestIO(i).fromRoq.wdata
+        difftest(i).wdst := soc.module.difftestIO(i).fromRoq.wdst
+        difftest(i).wpc := soc.module.difftestIO(i).fromRoq.wpc
+        difftest(i).scFailed := soc.module.difftestIO(i).fromRoq.scFailed
+        
+        difftest(i).r := soc.module.difftestIO(i).fromXSCore.r
+
+        difftest(i).intrNO := soc.module.difftestIO(i).fromCSR.intrNO
+        difftest(i).cause := soc.module.difftestIO(i).fromCSR.cause
+        difftest(i).priviledgeMode := soc.module.difftestIO(i).fromCSR.priviledgeMode
+        difftest(i).mstatus := soc.module.difftestIO(i).fromCSR.mstatus
+        difftest(i).sstatus := soc.module.difftestIO(i).fromCSR.sstatus
+        difftest(i).mepc := soc.module.difftestIO(i).fromCSR.mepc
+        difftest(i).sepc := soc.module.difftestIO(i).fromCSR.sepc
+        difftest(i).mtval := soc.module.difftestIO(i).fromCSR.mtval
+        difftest(i).stval := soc.module.difftestIO(i).fromCSR.stval
+        difftest(i).mtvec := soc.module.difftestIO(i).fromCSR.mtvec
+        difftest(i).stvec := soc.module.difftestIO(i).fromCSR.stvec
+        difftest(i).mcause := soc.module.difftestIO(i).fromCSR.mcause
+        difftest(i).scause := soc.module.difftestIO(i).fromCSR.scause
+        difftest(i).satp := soc.module.difftestIO(i).fromCSR.satp
+        difftest(i).mip := soc.module.difftestIO(i).fromCSR.mip
+        difftest(i).mie := soc.module.difftestIO(i).fromCSR.mie
+        difftest(i).mscratch := soc.module.difftestIO(i).fromCSR.mscratch
+        difftest(i).sscratch := soc.module.difftestIO(i).fromCSR.sscratch
+        difftest(i).mideleg := soc.module.difftestIO(i).fromCSR.mideleg
+        difftest(i).medeleg := soc.module.difftestIO(i).fromCSR.medeleg
+
+        difftest(i).storeCommit := soc.module.difftestIO(i).fromSQ.storeCommit
+        difftest(i).storeAddr := soc.module.difftestIO(i).fromSQ.storeAddr
+        difftest(i).storeData := soc.module.difftestIO(i).fromSQ.storeData
+        difftest(i).storeMask := soc.module.difftestIO(i).fromSQ.storeMask
+
+        difftest(i).sbufferResp := soc.module.difftestIO(i).fromSbuffer.sbufferResp
+        difftest(i).sbufferAddr := soc.module.difftestIO(i).fromSbuffer.sbufferAddr
+        difftest(i).sbufferData := soc.module.difftestIO(i).fromSbuffer.sbufferData
+        difftest(i).sbufferMask := soc.module.difftestIO(i).fromSbuffer.sbufferMask
+      }
+      io.difftest2 := difftest(1)
     }
 
     // BoringUtils.addSink(difftest.lrscAddr, "difftestLrscAddr")
-    io.difftest := difftest
+    io.difftest := difftest(0)
 
     val trap = WireInit(0.U.asTypeOf(new TrapIO))
     if (!env.FPGAPlatform) {
@@ -213,14 +270,19 @@ class XSSimTop(axiSim: Boolean)(implicit p: config.Parameters) extends LazyModul
 
   lazy val module = new LazyModuleImp(this) {
     val io = IO(new Bundle {
-      val difftest = new DiffTestIO
+      val difftest  = new DiffTestIO
+      val difftest2 = new DiffTestIO
       val logCtrl = new LogCtrlIO
       val trap = new TrapIO
       val uart = new UARTIO
       val memAXI = if (axiSim) chiselTypeOf(axiSimRam.module.io) else Input(Bool())
     })
+    io.difftest2 <> DontCare
 
-    io.difftest <> dut.module.io.difftest
+    io.difftest  <> dut.module.io.difftest
+    if (env.DualCoreDifftest) {
+      io.difftest2 <> dut.module.io.difftest2
+    }
     io.logCtrl <> dut.module.io.logCtrl
     io.trap <> dut.module.io.trap
     io.uart <> dut.module.io.uart