fix perf print, enable perf by default

src/main/scala/top/Parameters.scala

@@ -22,7 +22,7 @@ case class Parameters
 object Parameters {
   val dualCoreParameters = Parameters(socParameters = SoCParameters(NumCores = 2))
   val simParameters = Parameters(envParameters = EnviromentParameters(FPGAPlatform = false)) // sim only, disable log
-  val debugParameters = Parameters(envParameters = simParameters.envParameters.copy(EnableDebug = true)) // open log
+  val debugParameters = Parameters(envParameters = simParameters.envParameters.copy(EnableDebug = true, EnablePerfDebug = true)) // open log
 
   val simDualCoreParameters = Parameters(socParameters = SoCParameters(NumCores = 2), envParameters = EnviromentParameters(FPGAPlatform = false))
   val debugDualCoreParameters = Parameters(socParameters = SoCParameters(NumCores = 2), envParameters = simParameters.envParameters.copy(EnableDebug = true))

src/main/scala/utils/LogUtils.scala

@@ -108,16 +108,14 @@ object XSPerf {
     val next_counter = WireInit(0.U(64.W))
     val logTimestamp = WireInit(0.U(64.W))
     val enableDebug = Parameters.get.envParameters.EnableDebug
-    val logEnable = WireInit(false.B)
     next_counter := counter + perfCnt
     counter := next_counter
 
     if (enableDebug) {
-      ExcitingUtils.addSink(logEnable, "DISPLAY_LOG_ENABLE")
       ExcitingUtils.addSink(logTimestamp, "logTimestamp")
       val printCond =
         if(intervalBits == 0) true.B
-        else (logEnable && logTimestamp(intervalBits - 1, 0) === 0.U)
+        else (logTimestamp(intervalBits - 1, 0) === 0.U)
       when(printCond) { // TODO: Need print when program exit?
         if(acc) {
           XSLog(XSLogLevel.PERF)(true, true.B, p"$perfName, $next_counter\n")

src/main/scala/xiangshan/backend/CtrlBlock.scala

@@ -97,6 +97,8 @@ class RedirectGenerator extends XSModule with HasCircularQueuePtrHelper {
     redirect
   })
 
+  XSDebug(oldestExuOut.valid, p"exuMispredict: ${Binary(Cat(io.exuMispredict.map(_.valid)))}\n")
+
   val s1_isJump = RegNext(jumpIsOlder, init = false.B)
   val s1_jumpTarget = RegEnable(jumpOut.bits.redirect.cfiUpdate.target, jumpOut.valid)
   val s1_imm12_reg = RegEnable(oldestExuOut.bits.uop.ctrl.imm(11, 0), oldestExuOut.valid)

src/main/scala/xiangshan/backend/ftq/Ftq.scala

@@ -177,6 +177,6 @@ class Ftq extends XSModule with HasCircularQueuePtrHelper {
   XSPerf("mispredictRedirectAcc", io.redirect.valid && RedirectLevel.flushAfter === io.redirect.bits.level, acc = true)
   XSPerf("replayRedirectAcc", io.redirect.valid && RedirectLevel.flushItself(io.redirect.bits.level), acc = true)
 
-  XSDebug(io.commit_ftqEntry.valid, io.commit_ftqEntry.bits.toPrintable)
-  XSDebug(io.enq.fire(), io.enq.bits.toPrintable)
+  XSDebug(io.commit_ftqEntry.valid, p"ftq commit: ${io.commit_ftqEntry.bits}")
+  XSDebug(io.enq.fire(), p"ftq enq: ${io.enq.bits}")
 }