- 10 12月, 2021 1 次提交
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由 Yinan Xu 提交于
This commit optimizes the coding style and timing for hardware performance counters. By default, performance counters are RegNext(RegNext(_)).
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- 06 12月, 2021 1 次提交
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由 Jiawei Lin 提交于
* SoC: add axi4spliter * pmp: add apply method to reduce loc * pma: add PMA used in axi4's spliter * Fix package import * pma: re-write tl-pma, put tl-pma into AXI4Spliter * pma: add memory mapped pma * soc: rm dma port, rm axi4spliter, mv mmpma out of spliter * Remove unused files * update dma pma check port at SimTop.scala; update pll lock defalt value to 1 Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn> Co-authored-by: Nrvcoresjw <shangjiawei@rvcore.com>
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- 05 12月, 2021 1 次提交
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由 Yinan Xu 提交于
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- 04 12月, 2021 1 次提交
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由 Jay 提交于
* ICache: add ReplacePipe for Probe & Release * remove ProbeUnit * Probe & Release enter ReplacePipe * fix bugs when running Linux on MinimalConfig * TODO: set conflict for ReplacePipe * ICache: add Block logic for ReplacePipe * ReplacePipe: change probe assert condition * support Probe NToN (Probe not hit in ICache) * ICache: fix a bug in meta_write_arb
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- 30 11月, 2021 1 次提交
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由 William Wang 提交于
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- 29 11月, 2021 1 次提交
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由 William Wang 提交于
* sbuffer: do flush correctly while draining sbuffer * mem: disable EnableFastForward for timing reasons * sbuffer: optimize forward mask gen timing * dcache: block main pipe req if refill req is valid Refill req comes from refill arbiter. There is not time left for index conflict check. Now we block all main pipe req when refill req comes from miss queue. * dcache: delay some resp signals for better timing * dcache: optimize wbq enq entry select timing * dcache: decouple missq req.valid to valid & cancel * valid is fast, it is used to select which miss req will be sent to miss queue * cancel can be slow to generate, it will cancel miss queue req in the last moment * sbuffer: optimize noSameBlockInflight check timing
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- 28 11月, 2021 1 次提交
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由 Jay 提交于
* ICache: metaArray & dataArray use bank interleave * ICache: add bank interleave * ICache: add parity check for meta and data arrays * IFU: fix bug in secondary miss * secondary miss doesn't send miss request to miss queue * ICache: write back cancled miss request * ICacheMissEntry: add second miss merge * deal with situations that this entry has been flushed, and the next miss req just requests the same cachline. * ICache: add acquireBlock and GrantAck support * refact: move icache modules to frontend modules * ICache: add release surport and meta coh * ICache: change Get to AcquireBlock for A channel * rebuild: change ICachePara package for other file * ICache: add tilelogger for L1I * ICahce: add ProbeQueue and Probe Process Unit * ICache: add support for ProbeData * ICahceParameter: change tag code to ECC * ICahce: fix bugs in connect and ProbeUnit * metaArray/dataArray responses are not connected * ProbeUnit use reg so data and req are not synchronized * RealeaseUnit: write back mata when voluntary * Add ICache CacheInstruction * move ICache to xiangshan.frontend.icache._ * ICache: add CacheOpDecoder * change ICacheMissQueue to ICacheMissUnit * ProbeUnit: fix meta data not latch bug * IFU: delete releaseSlot and add missSlot * IFU: fix bugs in missSlot state machine * IFU: fix some bugs in miss Slot * IFU: move out fetch to ICache Array logic * ReleaseUnit: delete release write logic * MissUnit: send Release to ReleaseUnit after GAck * ICacheMainPipe: add mainpipe and stop logic * when f3_ready is low, stop the pipeline * IFU: move tlb and array access to mainpipe * Modify Frontend and ICache top for mainpipe * ReleaseUnit: add probe merge status register * ICache: add victim info and release in mainpipe * ICahche: add set-conflict logic * Release: do not invalid meta after sending release * bump Huancun: fix probe problem * bump huancun for MinimalConfig combinational loop * ICache: add LICENSE for new files * Chore: remove debug code and add perf counter * Bump huancun for bug fix * Bump HuanCun for alias bug * ICache: add dirty state for CliendMeta
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- 26 11月, 2021 1 次提交
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由 Yinan Xu 提交于
This commit changes how isFreed is calculated. Instead of using refCounter in the next, we compute it at this cycle and RegNext it.
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- 16 11月, 2021 1 次提交
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由 Jiawei Lin 提交于
* FDivSqrt: use hierarchy API to avoid dedup bug * Dedup: use hartId from io port instead of core parameters * Bump fudian
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- 13 11月, 2021 2 次提交
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由 Lingrui98 提交于
* fix a bug of wrongly discarding some new bits to be xored * ghr should be longer in default config to avoid falsely overriding * move TageBanks to top, and fix SC folded history config
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由 Lingrui98 提交于
* fix a bug of wrongly discarding some new bits to be xored * ghr should be longer in default config to avoid falsely overriding * move TageBanks to top, and fix SC folded history config
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- 12 11月, 2021 3 次提交
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由 Yinan Xu 提交于
* difftest: add basic difftest features for releases This commit adds basic difftest features for every release, no matter it's for simulation or physical design. The macro SYNTHESIS is used to skip these logics when synthesizing the design. This commit aims at allowing designs for physical design to be verified. * bump ready-to-run * difftest: add int and fp writeback data
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由 Lingrui98 提交于
* modify the largest history length to be 65 in order to avoid 2 level xors on speculative update * update ittage parameters to be an optimized one
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由 Lingrui98 提交于
bpu: bring folded history into use, and use previous ghr to do difftest; move tage and ittage config to top
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- 11 11月, 2021 3 次提交
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由 Lingrui98 提交于
* use compressed info to do redirects * implement folded history class
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由 Lemover 提交于
* tlb: timing optimization, when nWays is 1, divide hit and data(rm hitMux) * pmp: add param to control leave ParallelMux into next cycle, default n. The whole pmp match logic seems too long and takes more than a half cycle. Add this param and set it default false. * tlb: timing optimization, when level enable, move ppn gen to first cycle * tlb: fix bug of saveLevel and add it to TLBParameters
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由 Yinan Xu 提交于
* disable log as default * code clean up
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- 04 11月, 2021 1 次提交
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由 William Wang 提交于
* dcache: do not check readline rmask This should opt bank_conflict check timing * dcache: block replace if store s1 valid It takes quite long to generate way_en in mainpipe s1. As a result, use s1 way_en to judge if replace should be blocked will cause severe timing problem Now we simply block replace if mainpipe.s1.valid Refill timing to be optmized later * sbuffer: delay sbuffer enqueue for 1 cycle With store queue growing larger, read data from datamodule nearly costs a whole cycle. Hence we delay sbuffer enqueue for 1 cycle for better timing. * dcache: reduce probe queue size * dcache: replace probe pipe req RRArbiter with Arbiter * dcache: reduce writeback queue size for timing opt * dcache: delay wbqueue enqueue req for 1 cycle Addr enqueue req will compare its addr with addrs in all writeback entries to check if it should be blocked. Delay enqueue req will give that process more time. * dcache: set default replacer to setplru It does not change current design * dcache: fix wbqueue req_delayed deadlock We delayed writeback queue enq for 1 cycle, missQ req does not depend on wbQ enqueue. As a result, missQ req may be blocked in req_delayed. When grant comes, that req should also be updated * dcache: remove outdated require * dcache: replace missReqArb RRArbiter with Arbiter * perf: add detailed histogram for low dcache latency * dcache: fix wbqueue entry alloc logic * dcache: opt probe req timing In current design, resv_set is maintained in dcache. All probe req will be blocked if that addr is in resv_set. However, checking if that addr is in resv_set costs almost half a cycle, which causes severe timing problem. Now when we update update_resv_set, all probe reqs will be blocked in the next cycle. It should give Probe reservation set addr compare an independent cycle, which will lead to better timing
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- 30 10月, 2021 2 次提交
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由 Yinan Xu 提交于
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由 Jiawei Lin 提交于
* Add cache ctrl node * L2/L3: Reduce client dir size * Ctrl: connect soft reset from L3 to core * Add pll * Config: seperate SocParams and CoreParams to get correct number of cores * Bump huancun * Add pll output * Fix inclusive cache config * Add one more pll ctrl reg * Bump huancun
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- 29 10月, 2021 1 次提交
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由 William Wang 提交于
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- 25 10月, 2021 1 次提交
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由 Lemover 提交于
remove the old hard-wired pma and turn to pmp-like csr registers. the pma config is writen in pma register. 1. pma are m-priv csr, so only m-mode csrrw can change pma 2. even in m-mode, pma should be always checked, no matter lock or not 3. so carefully write pma, make sure not to "suicide" * pma: add pmp-like pma, just module/bundle added, not to circuit use reserved 2 bits as atomic and cached * pma: add pmp-like pma into pmp module pma have two more attribute than pmp 1. atmoic; 2. c/cache, if false, go to mmio. pma uses 16+4 machine-level custom ready write csr. pma will always be checked even in m-mode. * pma: remove the old MemMap in tlb, mmio arrives next cycle * pma: ptw raise af when mmio * pma: fix bug of match's zip with last entry * pma: fix bug of pass reset signal through method's parameter strange bug, want to reset, pass reset signal to a method, does not work. import chisel3.Module.reset, the method can access reset it's self. * pma: move some method to trait and fix bug of pma_init value * pma: fix bug of pma init value assign way * tlb: fix stupid bug that pf.ld not & fault_valid * loadunit: fix bug that uop is flushed, pmp's dcache kill failed also * ifu: mmio access needs f2_valid now * loadunit: if mmio and have sent fastUop, flush pipe when commit * storeunit: stu->lsq at stage1 and re-in lsq at stage2 to update mmio
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- 23 10月, 2021 1 次提交
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由 rvcoresjw 提交于
* Add perf counters * add reg from hpm counter source * add print perfcounter enable
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- 22 10月, 2021 1 次提交
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由 William Wang 提交于
* mem: support ld-ld violation check * mem: do not fast wakeup if ld vio check failed * mem: disable ld-ld vio check after core reset
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- 21 10月, 2021 1 次提交
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由 happy-lx 提交于
add mmu's asid support. 1. put asid inside sram (if the entry is sram), or it will take too many sources. 2. when sfence, just flush it all, don't care asid. 3. when hit check, check asid. 4. when asid changed, flush all the inflight ptw req for safety 5. simple asid unit test: asid 1 write, asid 2 read and check, asid 2 write, asid 1 read and check. same va, different pa * ASID: make satp's asid bits configurable to RW * use AsidLength to control it * ASID: implement asid refilling and hit checking * TODO: sfence flush with asid * ASID: implement sfence with asid * TODO: extract asid from SRAMTemplate * ASID: extract asid from SRAMTemplate * all is down * TODO: test * fix write to asid * Sfence: support rs2 of sfence and fix Fence Unit * rs2 of Sfence should be Reg and pass it to Fence Unit * judge the value of reg instead of the index in Fence Unit * mmu: re-write asid now, asid is stored inside sram, so sfence just flush it it's a complex job to handle the problem that asid is changed but no sfence.vma is executed. when asid is changed, all the inflight mmu reqs are flushed but entries in storage is not influenced. so the inflight reqs do not need to record asid, just use satp.asid * tlb: fix bug of refill mask * ci: add asid unit test Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn>
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- 20 10月, 2021 1 次提交
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由 zhanglinjuan 提交于
* L1D: provide independent meta array for load pipe * misc: reorg files in cache dir * chore: reorg l1d related files * bump difftest: use clang to compile verialted files * dcache: add BankedDataArray * dcache: fix data read way_en * dcache: fix banked data wmask * dcache: replay conflict correctly When conflict is detected: * Report replay * Disable fast wakeup * dcache: fix bank addr match logic * dcache: add bank conflict perf counter * dcache: fix miss perf counters * chore: make lsq data print perttier * dcache: enable banked ecc array * dcache: set dcache size to 128KB * dcache: read mainpipe data from banked data array * dcache: add independent mainpipe data read port * dcache: revert size change * Size will be changed after main pipe refactor * Merge remote-tracking branch 'origin/master' into l1-size * dcache: reduce banked data load conflict * MainPipe: ReleaseData for all replacement even if it's clean * dcache: set dcache size to 128KB BREAKING CHANGE: l2 needed to provide right vaddr index to probe l1, and it has to help l1 to avoid addr alias problem * chore: fix merge conflict * Change L2 to non-inclusive / Add alias bits in L1D * debug: hard coded dup data array for debuging * dcache: fix ptag width * dcache: fix amo main pipe req * dcache: when probe, use vaddr for main pipe req * dcache: include vaddr in atomic unit req * dcache: fix get_tag() function * dcache: fix writeback paddr * huancun: bump version * dcache: erase block offset bits in release addr * dcache: do not require probe vaddr != 0 * dcache: opt banked data read timing * bump huancun * dcache: fix atom unit pipe req vaddr * dcache: simplify main pipe writeback_vaddr * bump huancun * dcache: remove debug data array * Turn on all usr bits in L1 * Bump huancun * Bump huancun * enable L2 prefetcher * bump huancun * set non-inclusive L2/L3 + 128KB L1 as default config * Use data in TLBundleB to hint ProbeAck beeds data * mmu.l2tlb: mem_resp now fills multi mq pte buffer mq entries can just deq without accessing l2tlb cache * dcache: handle dirty userbit * bump huancun * chore: l1 cache code clean up * Remove l1plus cache * Remove HasBankedDataArrayParameters * Add bus pmu between L3 and Mem * bump huncun * IFU: add performance counters and mmio af * icache replacement policy moniter * ifu miss situation moniter * icache miss rate * raise access fault when found mmio req * Add framework for seperated main pipe and reg meta array * Rewrite miss queue for seperated pipes * Add RefillPipe * chore: rename NewSbuffer.scala * cache: add CacheInstruction opcode and reg list * CSR: add cache control registers * Add Replace Pipe * CacheInstruction: add CSRs for cache instruction * mem: remove store replay unit * Perf counter to be added * Timing opt to be done * mem: update sbuffer to support new dcache * sbuffer: fix missqueue time out logic * Merge remote-tracking branch 'origin/master' into dcache-rm-sru * chore: fix merge conflict, remove nStoreReplayEntries * Temporarily disable TLMonitor * Bump huancun (L2/L3 MSHR bug fix) * Rewrite main pipe * ReplacePipe: read meta to decide whether data should be read * RefillPipe: add a store resp port * MissQueue: new req should be rejected according to set+way * Add replacement policy interface * sbuffer: give missq replay the highest priority Now we give missqReplayHasTimeOut the highest priority, as eviction has already happened Besides, it will fix the problem that fix dcache eviction generate logic gives the wrong sbuffer id * Finish DCache framework * Split meta & tag and use regs to build meta array * sbuffer: use new dcache io * dcache: update dcache resp in memblock and fake d$ * Add atomics processing flow * Refactor Top * Bump huancun * DCacheWrapper: disable ld fast wakeup only when bank conflict * sbuffer: update dcache_resp difftest io * MainPipe: fix combinational loop * Sbuffer: fix bug in assert * RefillPipe: fix bug of getting tag from addr * dcache: ~0.U should restrict bit-width * LoadPipe: fix bug in assert * ReplacePipe: addr to be replaced should be block-aligned * MainPipe: fix bug in required coh sending to miss queue * DCacheWrapper: tag write in refill pipe should always be ready * MainPipe: use replacement way_en when the req is from miss queue * MissQueue: refill data should be passed on to main pipe * MainPipe: do not use replacement way when tag match * CSR: clean up cache op regs * chore: remove outdated comments * ReplacePipe: fix stupid bug * dcache: replace checkOneHot with assert * alu: fix bug of rev8 & orc.b instruction * MissQueue: fix bug in the condition of mshr accepting a req * MissQueue: add perf counters * chore: delete out-dated code * chore: add license * WritebackQueue: distinguish id from miss queue * AsynchronousMetaArray: fix bug * Sbuffer: fix difftest io * DCacheWrapper: duplicate one more tag copy for main pipe * Add perf cnt to verify whether replacing is too early * dcache: Release needs to wait for refill pipe * WritebackQueue: fix accept condition * MissQueue: remove unnecessary assert * difftest: let refill check ingore illegal mem access * Parameters: enlarge WritebackQueue to break dead-lock * DCacheWrapper: store hit wirte should not be interrupted by refill * Config: set nReleaseEntries to twice of nMissEntries * DCacheWrapper: main pipe read should block refill pipe by set Co-authored-by: NWilliam Wang <zeweiwang@outlook.com> Co-authored-by: NLinJiawei <linjiav@outlook.com> Co-authored-by: NTangDan <tangdan@ict.ac.cn> Co-authored-by: NLinJiawei <linjiawei20s@ict.ac.cn> Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn> Co-authored-by: Nwangkaifan <wangkaifan@ict.ac.cn> Co-authored-by: NJinYue <jinyue20s@ict.ac.cn> Co-authored-by: Zhangfw <471348957@qq.com>
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- 16 10月, 2021 1 次提交
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由 Yinan Xu 提交于
This commit optimizes the move elimination implementation. Reference counting for every physical register is recorded. Originally 0-31 registers have counters of ones. Every time the physical register is allocated or deallocated, the counter is increased or decreased by one. When the counter becomes zero from a non-zero value, the register is freed and released to freelist.
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- 14 10月, 2021 1 次提交
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由 Lingrui98 提交于
frontendBundle: add chiselName annotation for bundles, code clean ups and timing optimization (hopefully)
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- 11 10月, 2021 1 次提交
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由 Lemover 提交于
* [WIP] PMP: add pmp to tlb & csr(ptw part is not added) * pmp: add pmp, unified * pmp: add pmp, distributed but same cycle * pmp: pmp resp next cycle * [WIP] PMP: add l2tlb missqueue pmp support * pmp: add pmp to ptw and regnext pmp for frontend * pmp: fix bug of napot-match * pmp: fix bug of method aligned * pmp: when write cfg, update mask * pmp: fix bug of store af getting in store unit * tlb: fix bug, add af check(access fault from ptw) * tlb: af may have higher priority than pf when ptw has af * ptw: fix bug of sending paddr to pmp and recv af * ci: add pmp unit test * pmp: change PMPPlatformGrain to 6 (512bits) * pmp: fix bug of read_addr * ci: re-add pmp unit test * l2tlb: lazymodule couldn't use @chiselName * l2tlb: fix bug of l2tlb missqueue duplicate req's logic filt the duplicate req: old: when enq, change enq state to different state new: enq + mem.req.fire, more robust * pmp: pmp checker now supports samecycle & regenable
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- 10 10月, 2021 1 次提交
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由 Yinan Xu 提交于
This commit optimizes RenameTable's timing. Read addresses come from instruction buffer directly and has best timing. So we let data read at decode stage and bypass write data from this clock cycle to the read data at next cycle. For write, we latch the write request and process it at the next cycle.
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- 01 10月, 2021 1 次提交
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由 Yinan Xu 提交于
This commit moves load/store reservation stations into the first ExuBlock (or calling it IntegerBlock). The unnecessary dispatch module is also removed from CtrlBlock. Now the module organization becomes: * ExuBlock: Int RS, Load/Store RS, Int RF, Int FUs * ExuBlock_1: Fp RS, Fp RF, Fp FUs * MemBlock: Load/Store FUs Besides, load queue has 80 entries and store queue has 64 entries now.
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- 30 9月, 2021 2 次提交
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由 Jiawei Lin 提交于
* Refactor cache params * L2: support multi-bank * fix l2 size * remove 'IgnoreNode' * bump difftest and huancun
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由 Jiawei Lin 提交于
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- 28 9月, 2021 2 次提交
- 27 9月, 2021 1 次提交
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由 Jiawei Lin 提交于
* L1D: provide independent meta array for load pipe * misc: reorg files in cache dir * chore: reorg l1d related files * bump difftest: use clang to compile verialted files * dcache: add BankedDataArray * dcache: fix data read way_en * dcache: fix banked data wmask * dcache: replay conflict correctly When conflict is detected: * Report replay * Disable fast wakeup * dcache: fix bank addr match logic * dcache: add bank conflict perf counter * dcache: fix miss perf counters * chore: make lsq data print perttier * dcache: enable banked ecc array * dcache: set dcache size to 128KB * dcache: read mainpipe data from banked data array * dcache: add independent mainpipe data read port * dcache: revert size change * Size will be changed after main pipe refactor * Merge remote-tracking branch 'origin/master' into l1-size * dcache: reduce banked data load conflict * MainPipe: ReleaseData for all replacement even if it's clean * dcache: set dcache size to 128KB BREAKING CHANGE: l2 needed to provide right vaddr index to probe l1, and it has to help l1 to avoid addr alias problem * chore: fix merge conflict * Change L2 to non-inclusive / Add alias bits in L1D * debug: hard coded dup data array for debuging * dcache: fix ptag width * dcache: fix amo main pipe req * dcache: when probe, use vaddr for main pipe req * dcache: include vaddr in atomic unit req * dcache: fix get_tag() function * dcache: fix writeback paddr * huancun: bump version * dcache: erase block offset bits in release addr * dcache: do not require probe vaddr != 0 * dcache: opt banked data read timing * bump huancun * dcache: fix atom unit pipe req vaddr * dcache: simplify main pipe writeback_vaddr * bump huancun * dcache: remove debug data array * Turn on all usr bits in L1 * Bump huancun * Bump huancun * enable L2 prefetcher * bump huancun * set non-inclusive L2/L3 + 128KB L1 as default config * Use data in TLBundleB to hint ProbeAck beeds data * mmu.l2tlb: mem_resp now fills multi mq pte buffer mq entries can just deq without accessing l2tlb cache * dcache: handle dirty userbit * bump huancun * chore: l1 cache code clean up * Remove l1plus cache * Remove HasBankedDataArrayParameters * Add bus pmu between L3 and Mem * bump huncun * dcache: fix l1 probe index generate logic * Now right probe index will be used according to the len of alias bits * dcache: clean up amo pipeline * DCacheParameter rowBits will be removed in the future, now we set it to 128 to make dcache work * dcache: fix amo word index * bump huancun Co-authored-by: NWilliam Wang <zeweiwang@outlook.com> Co-authored-by: Nzhanglinjuan <zhanglinjuan20s@ict.ac.cn> Co-authored-by: NTangDan <tangdan@ict.ac.cn> Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn> Co-authored-by: Nwangkaifan <wangkaifan@ict.ac.cn>
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- 15 9月, 2021 1 次提交
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由 Lemover 提交于
nothing changed but add one parameter to control if ldtlb and sttlb are the same now there two similar parameters: outReplace: when this is true, two ldtlb are 'same', two sttlb are 'same' refillBothTlb: when this is true, the four tlb are same(require outReplace to be true) * mmu.tlb: add param refillBothTlb to refill both ld & st tlb * mmu.tlb: set param refillBothTlb to false
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- 10 9月, 2021 1 次提交
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由 Jiawei Lin 提交于
* misc: add submodule huancun * huancun: integrate huancun to SoC as L3 * remove l2prefetcher * update huancun * Bump HuanCun * Use HuanCun instead old L2/L3 * bump huancun * bump huancun * Set L3NBanks to 4 * Update rocketchip * Bump huancun * Bump HuanCun * Optimize debug configs * Configs: fix L3 bug * Add TLLogger * TLLogger: fix release ack address * Support write prefix into database * Recoding more tilelink info * Add a database output format converter * missqueue: add difftest port for memory difftest during refill * misc: bump difftest * misc: bump difftest & huancun * missqueue: do not check refill data when get Grant * Add directory debug tool * config: increase client dir size for non-inclusive cache * Bump difftest and huancun * Update l2/l3 cache configs * Remove deprecated fpga/* * Remove cache test * Remove L2 preftecher * bump huancun * Params: turn on l2 prefetch by default * misc: remove duplicate chisel-tester2 * misc: remove sifive inclusive cache * bump difftest * bump huancun * config: use 4MB L3 cache * bump huancun * bump difftest * bump difftest Co-authored-by: Nwangkaifan <wangkaifan@ict.ac.cn> Co-authored-by: NTangDan <tangdan@ict.ac.cn>
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- 09 9月, 2021 1 次提交
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由 Lemover 提交于
* mmu.tlb: l2tlb's l3 now 128 sets and 4 ways * mmu.tlb: set itlb default size
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- 06 9月, 2021 1 次提交
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由 YikeZhou 提交于
* backend, rename: support elimination of mv inst whose lsrc=0 [known bug] instr page fault not properly raised after sfence.vma * backend, roq: [bug fix] won't label me with exception as writebacked
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