* misc: soc timing optimize

* XSTile: insert buffer between L1Dcache and L2

* FDivSqrt: use hierarchy API to avoid dedup bug

* Dedup: use hartId from io port instead of core parameters

* Bump fudian

This bug happens when a branch prediction results in a fetch to MMIO space, and the backend flush could not flush the MMIO, thus results in blocking.

DCache timing problem has not been solved yet. DCache structure will be further changed.

* sbuffer: add extra perf counters

* sbuffer: optmize timeout replay check timing

* sbuffer: optmize do_uarch_drain check timing

Now we only compare merge entry's vtag, check will not start until
mergeIdx is generated by PriorityEncoder

* mem, lq: optmize writeback select logic timing

* dcache: replace missqueue reill req arbiter

* dcache: refactor missqueue entry select logic

* mem: add comments for lsq data

* dcache: give amo alu an extra cycle

* sbuffer: optmize sbuffer forward data read timing

* Untested Trigger Implementation
Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>
Co-authored-by: NLingrui98 <goulingrui19s@ict.ac.cn>
Co-authored-by: Nrvcoresjw <shangjiawei@rvcore.com>

* assuming that beyond fetch => oversize

* fix a bug of wrongly discarding some new bits to be xored
* ghr should be longer in default config to avoid falsely overriding
* move TageBanks to top, and fix SC folded history config

* FDivSqrt: replace hardfloat by fudian

* use pipeline branch for fudian

* fix a bug of wrongly discarding some new bits to be xored
* ghr should be longer in default config to avoid falsely overriding
* move TageBanks to top, and fix SC folded history config

* difftest: add basic difftest features for releases

This commit adds basic difftest features for every release, no matter
it's for simulation or physical design. The macro SYNTHESIS is used to
skip these logics when synthesizing the design. This commit aims at
allowing designs for physical design to be verified.

* bump ready-to-run

* difftest: add int and fp writeback data

* modify the largest history length to be 65 in order to avoid
  2 level xors on speculative update

* update ittage parameters to be an optimized one

bpu: bring folded history into use, and use previous ghr to do difftest; move tage and ittage config to top

It will help difftest skip hpm CSR access correctly

* use compressed info to do redirects
* implement folded history class

* tlb: timing optimization, when nWays is 1, divide hit and data(rm hitMux)

* pmp: add param to control leave ParallelMux into next cycle, default n.

The whole pmp match logic seems too long and takes more than
a half cycle.
Add this param and set it default false.

* tlb: timing optimization, when level enable, move ppn gen to first cycle

* tlb: fix bug of saveLevel and add it to TLBParameters

* disable log as default
* code clean up

* PreDecode: fix beyond fetch bug

* Fallthrough address === startAddress + 34 Bytes and the 17th 2 Bytes is an RVC instruction, which will be missing when sending to ibuffer

* PreDecode: fix target when beyond fetch happen

* SoC: change buffer latency && set L3 size to 8MB

* BinaryArbiter: fix bugs when iknow < 4

This fixes differences between the pingpong bits in ctrlblock and dispatch2.