- 23 11月, 2021 1 次提交
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由 Yinan Xu 提交于
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- 21 11月, 2021 1 次提交
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由 Jiawei Lin 提交于
* misc: soc timing optimize * XSTile: insert buffer between L1Dcache and L2
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- 17 11月, 2021 1 次提交
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由 Li Qianruo 提交于
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- 16 11月, 2021 4 次提交
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由 Lingrui98 提交于
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由 zhanglinjuan 提交于
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由 Jiawei Lin 提交于
* FDivSqrt: use hierarchy API to avoid dedup bug * Dedup: use hartId from io port instead of core parameters * Bump fudian
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由 Jay 提交于
This bug happens when a branch prediction results in a fetch to MMIO space, and the backend flush could not flush the MMIO, thus results in blocking.
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- 15 11月, 2021 5 次提交
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由 wakafa 提交于
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由 zoujr 提交于
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由 William Wang 提交于
DCache timing problem has not been solved yet. DCache structure will be further changed. * sbuffer: add extra perf counters * sbuffer: optmize timeout replay check timing * sbuffer: optmize do_uarch_drain check timing Now we only compare merge entry's vtag, check will not start until mergeIdx is generated by PriorityEncoder * mem, lq: optmize writeback select logic timing * dcache: replace missqueue reill req arbiter * dcache: refactor missqueue entry select logic * mem: add comments for lsq data * dcache: give amo alu an extra cycle * sbuffer: optmize sbuffer forward data read timing
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由 zhanglinjuan 提交于
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由 Li Qianruo 提交于
* Untested Trigger Implementation Co-authored-by: NWilliam Wang <zeweiwang@outlook.com> Co-authored-by: NLingrui98 <goulingrui19s@ict.ac.cn> Co-authored-by: Nrvcoresjw <shangjiawei@rvcore.com>
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- 14 11月, 2021 2 次提交
- 13 11月, 2021 3 次提交
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由 Lingrui98 提交于
* fix a bug of wrongly discarding some new bits to be xored * ghr should be longer in default config to avoid falsely overriding * move TageBanks to top, and fix SC folded history config
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由 Fawang Zhang 提交于
* FDivSqrt: replace hardfloat by fudian * use pipeline branch for fudian
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由 Lingrui98 提交于
* fix a bug of wrongly discarding some new bits to be xored * ghr should be longer in default config to avoid falsely overriding * move TageBanks to top, and fix SC folded history config
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- 12 11月, 2021 10 次提交
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由 Yinan Xu 提交于
* difftest: add basic difftest features for releases This commit adds basic difftest features for every release, no matter it's for simulation or physical design. The macro SYNTHESIS is used to skip these logics when synthesizing the design. This commit aims at allowing designs for physical design to be verified. * bump ready-to-run * difftest: add int and fp writeback data
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由 zoujr 提交于
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由 zoujr 提交于
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由 Yinan Xu 提交于
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由 Lingrui98 提交于
* modify the largest history length to be 65 in order to avoid 2 level xors on speculative update * update ittage parameters to be an optimized one
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由 Lingrui98 提交于
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由 Lingrui98 提交于
bpu: bring folded history into use, and use previous ghr to do difftest; move tage and ittage config to top
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由 ZhangZifei 提交于
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由 ZhangZifei 提交于
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由 ZhangZifei 提交于
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- 11 11月, 2021 5 次提交
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由 William Wang 提交于
It will help difftest skip hpm CSR access correctly
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由 Lingrui98 提交于
* use compressed info to do redirects * implement folded history class
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由 ZhangZifei 提交于
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由 Lemover 提交于
* tlb: timing optimization, when nWays is 1, divide hit and data(rm hitMux) * pmp: add param to control leave ParallelMux into next cycle, default n. The whole pmp match logic seems too long and takes more than a half cycle. Add this param and set it default false. * tlb: timing optimization, when level enable, move ppn gen to first cycle * tlb: fix bug of saveLevel and add it to TLBParameters
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由 Yinan Xu 提交于
* disable log as default * code clean up
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- 10 11月, 2021 2 次提交
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由 wakafa 提交于
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由 Fawang Zhang 提交于
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- 09 11月, 2021 5 次提交
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由 rvcoresjw 提交于
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由 rvcoresjw 提交于
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由 Jay 提交于
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由 Jay 提交于
* PreDecode: fix beyond fetch bug * Fallthrough address === startAddress + 34 Bytes and the 17th 2 Bytes is an RVC instruction, which will be missing when sending to ibuffer * PreDecode: fix target when beyond fetch happen
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由 Jiawei Lin 提交于
* SoC: change buffer latency && set L3 size to 8MB * BinaryArbiter: fix bugs when iknow < 4
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- 07 11月, 2021 1 次提交
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由 Yinan Xu 提交于
This fixes differences between the pingpong bits in ctrlblock and dispatch2.
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