- 29 10月, 2019 1 次提交
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由 zhanglinjuan 提交于
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- 22 10月, 2019 1 次提交
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由 zhanglinjuan 提交于
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- 14 10月, 2019 2 次提交
- 10 10月, 2019 1 次提交
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由 Zihao Yu 提交于
noop,Cache: support no dcache See merge request projectn/noop!32
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- 09 10月, 2019 7 次提交
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
Icache mmio See merge request projectn/noop!31
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
* For 1toN crossbar, the in.req.addr will change once the request is accepted. When there are multiple output channels, this may cause outSelIdx to change before receiving the response. Latching outSelIdx solves this issue.
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
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- 08 10月, 2019 5 次提交
- 07 10月, 2019 13 次提交
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由 Zihao Yu 提交于
noop: support no dcache See merge request projectn/noop!29
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
Intr See merge request projectn/noop!28
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
* now vivado reports good timing across clock domains
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由 Zihao Yu 提交于
Set associate See merge request projectn/noop!27
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
* IPC: 0.532621 -> 0.535300
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
* Now we should read 8 times to fetch a whole cache line to writeback to memory. This seems a lot IPC degradation in emu: 0.543329 -> 0.532621. But it does not hurt too much on FPGA. * Temporarily disable coherency.
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- 06 10月, 2019 4 次提交
- 05 10月, 2019 6 次提交