Merge branch 'fix-no-dcache' into 'master'

noop,Cache: support no dcache

See merge request projectn/noop!32

src/main/scala/noop/Cache.scala

@@ -450,11 +450,21 @@ class Cache(implicit val cacheConfig: CacheConfig) extends CacheModule {
 }
 
 object Cache {
-  def apply(in: SimpleBusUC, mmio: SimpleBusUC, flush: UInt)(implicit cacheConfig: CacheConfig) = {
-    val cache = Module(new Cache)
-    cache.io.flush := flush
-    cache.io.in <> in
-    mmio <> cache.io.mmio
-    cache.io.out
+  def apply(in: SimpleBusUC, mmio: SimpleBusUC, flush: UInt, enable: Boolean = true)(implicit cacheConfig: CacheConfig) = {
+    if (enable) {
+      val cache = Module(new Cache)
+        cache.io.flush := flush
+      cache.io.in <> in
+      mmio <> cache.io.mmio
+      cache.io.out
+    } else {
+      val addrspace = List(AddressSpace.dram) ++ AddressSpace.mmio
+      val xbar = Module(new SimpleBusCrossbar1toN(addrspace))
+      val busC = WireInit(0.U.asTypeOf(new SimpleBusC))
+      busC.mem <>xbar.io.out(0)
+      xbar.io.in <> in
+      mmio <> xbar.io.out(1)
+      busC
+    }
   }
 }

src/main/scala/noop/NOOP.scala

@@ -83,6 +83,6 @@ class NOOP(implicit val p: NOOPConfig) extends NOOPModule {
   val mmioXbar = Module(new SimpleBusCrossbarNto1(2))
   io.imem <> Cache(ifu.io.imem, mmioXbar.io.in(0), Fill(2, ifu.io.flushVec(0) | ifu.io.bpFlush))(
     CacheConfig(ro = true, name = "icache", userBits = AddrBits*2))
-  io.dmem <> Cache(exu.io.dmem, mmioXbar.io.in(1), "b00".U)(CacheConfig(ro = false, name = "dcache"))
+  io.dmem <> Cache(exu.io.dmem, mmioXbar.io.in(1), "b00".U, enable = HasDcache)(CacheConfig(ro = false, name = "dcache"))
   io.mmio <> mmioXbar.io.out
 }