README.md

    XiangShan

    XiangShan (香山) is an open-source high-performance RISC-V processor project.

    中文说明在此

    Copyright 2020-2022 by Institute of Computing Technology, Chinese Academy of Sciences.

    Copyright 2020-2022 by Peng Cheng Laboratory.

    Docs and slides

    XiangShan-doc is our official documentation repository. It contains design spec., technical slides, tutorial and more.

    Publications

    MICRO 2022: Towards Developing High Performance RISC-V Processors Using Agile Methodology

    Our paper introduces XiangShan and the practice of agile development methodology on high performance RISC-V processors. It covers some representative tools we have developed and used to accelerate the chip development process, including design, functional verification, debugging, performance validation, etc. This paper is awarded all three available badges for artifact evaluation (Available, Functional, and Reproduced).

    Artifacts Available Artifacts Evaluated — Functional Results Reproduced

    Paper PDF | IEEE Xplore | BibTeX | Presentation Slides | Presentation Video

    Follow us

    Wechat/微信:香山开源处理器

    Zhihu/知乎:香山开源处理器

    Weibo/微博:香山开源处理器

    You can contact us through our mail list. All mails from this list will be archived to here.

    Architecture

    The first stable micro-architecture of XiangShan is called Yanqihu (雁栖湖) on the yanqihu branch, which has been developed since June 2020.

    The second stable micro-architecture of XiangShan is called Nanhu (南湖) on the nanhu branch.

    The current version of XiangShan, also known as Kunminghu (昆明湖), is still under development on the master branch.

    The micro-architecture overview of Nanhu (南湖) is shown below.

    xs-arch-nanhu

    Sub-directories Overview

    Some of the key directories are shown below.

    .
    ├── src
    │   └── main/scala         # design files
    │       ├── device         # virtual device for simulation
    │       ├── system         # SoC wrapper
    │       ├── top            # top module
    │       ├── utils          # utilization code
    │       ├── xiangshan      # main design code
    │       └── xstransforms   # some useful firrtl transforms
    ├── scripts                # scripts for agile development
    ├── fudian                 # floating unit submodule of XiangShan
    ├── huancun                # L2/L3 cache submodule of XiangShan
    ├── difftest               # difftest co-simulation framework
    └── ready-to-run           # pre-built simulation images

    IDE Support

    bsp

    make bsp

    IDEA

    make idea

    Generate Verilog

    • Run make verilog to generate verilog code. The output file is build/XSTop.v.
    • Refer to Makefile for more information.

    Run Programs by Simulation

    Prepare environment

    • Set environment variable NEMU_HOME to the absolute path of the NEMU project.
    • Set environment variable NOOP_HOME to the absolute path of the XiangShan project.
    • Set environment variable AM_HOME to the absolute path of the AM project.
    • Install mill. Refer to the Manual section in this guide.
    • Clone this project and run make init to initialize submodules.

    Run with simulator

    • Install Verilator, the open-source Verilog simulator.
    • Run make emu to build the C++ simulator ./build/emu with Verilator.
    • Refer to ./build/emu --help for run-time arguments of the simulator.
    • Refer to Makefile and verilator.mk for more information.

    Example:

    make emu CONFIG=MinimalConfig EMU_THREADS=2 -j10
    ./build/emu -b 0 -e 0 -i ./ready-to-run/coremark-2-iteration.bin --diff ./ready-to-run/riscv64-nemu-interpreter-so

    Troubleshooting Guide

    Troubleshooting Guide

    Acknowledgement

    In the development of XiangShan, some sub-modules from the open-source community are employed. All relevant usage is listed below.

    Sub-module Source Detail
    L2 Cache/LLC Sifive block-inclusivecache Our new L2/L3 design are inspired by Sifive's block-inclusivecache.
    Diplomacy/TileLink Rocket-chip We reused the Diplomacy framework and TileLink utility that exist in rocket-chip to negotiate bus.

    We are grateful for the support of the open-source community and encourage other open-source projects to reuse our code within the scope of the license.

    项目简介

    Open-source high-performance RISC-V processor

    🚀 Github 镜像仓库 🚀

    源项目地址

    https://github.com/OpenXiangShan/XiangShan

    发行版本

    当前项目没有发行版本

    贡献者 66

    全部贡献者

    开发语言

    • Scala 94.0 %
    • Python 4.5 %
    • Shell 0.6 %
    • Makefile 0.5 %
    • C 0.4 %