diff --git a/src/main/scala/xiangshan/Parameters.scala b/src/main/scala/xiangshan/Parameters.scala
index 1dbbab760b2ebbcd6316973071e6669678824ee9..69711223cd640aa74a3517409da2ca620eb05c50 100644
--- a/src/main/scala/xiangshan/Parameters.scala
+++ b/src/main/scala/xiangshan/Parameters.scala
@@ -148,7 +148,9 @@ case class XSCoreParameters
     fetchi = true,
     useDmode = false,
     sameCycle = true,
+    normalNWays = 32,
     normalReplacer = Some("plru"),
+    superNWays = 4,
     superReplacer = Some("plru"),
     shouldBlock = true
   ),
diff --git a/src/main/scala/xiangshan/cache/mmu/MMUConst.scala b/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
index 3d08820a1b86a35608acb71898f26a2c491a6f43..777f0e45ddf37b1178d966abb5f4a19e0ab37b00 100644
--- a/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
+++ b/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
@@ -56,8 +56,8 @@ case class L2TLBParameters
   l2nWays: Int = 4,
   l2Replacer: Option[String] = Some("setplru"),
   // l3
-  l3nSets: Int = 64,
-  l3nWays: Int = 8,
+  l3nSets: Int = 128,
+  l3nWays: Int = 4,
   l3Replacer: Option[String] = Some("setplru"),
   // sp
   spSize: Int = 16,